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    Charge pump phase locked loop with improved power supply rejection
    2.
    发明授权
    Charge pump phase locked loop with improved power supply rejection 有权
    充电泵锁相环，具有改进的电源抑制

    公开(公告)号：US06963233B2

    公开(公告)日：2005-11-08

    申请号：US10793367

    申请日：2004-03-03

    申请人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    发明人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/18

    CPC分类号： H03L7/0895 ,  H03L7/18

    摘要： A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

    摘要翻译： 锁相环电路（60）具有相位频率检测器（62），电荷泵（64），有源滤波器（87）和压控振荡器（100）。 相位检测器响应于参考信号F SUB和VCO输出信号F OUT产生信号。 电荷泵根据相位检测器信号的值在第一传输门（76）的输入端产生电压。 在第二传输门（112）的输入处产生预定电压。 当传输门（76,110）闭合（低阻抗）时，电荷泵可以将有源滤波器86的运算放大器（86）的反相输入端的电流吸收或输出，并将预定的电压施加到非反相 输入。 当传输门打开（高阻抗状态）时，反相输入与节点电隔离，非反相输出与电源隔离。

    Interlaced master-slave ECL D flip-flop
    5.
    发明授权
    Interlaced master-slave ECL D flip-flop 有权
    隔行主从ECL D触发器

    公开(公告)号：US06191629B1

    公开(公告)日：2001-02-20

    申请号：US09405964

    申请日：1999-09-27

    申请人： Biagio Bisanti ,  Akbar Ali

    发明人： Biagio Bisanti ,  Akbar Ali

    IPC分类号： H03K3289

    CPC分类号： H03K3/2885 ,  H03K3/289

    摘要： A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.

    摘要翻译： 提供了具有低功耗并且能够高速运行的主从配置工作的D触发器电路，并且提供了一种降低这种电路中的功耗的方法。 电路实施例包括两个锁存器，每个锁存器具有开关和存储器部分以及两个隔行电流源。 响应于活动的高时钟信号，主锁存存储器部分使用来自第一电流源的电流，而从锁存器切换部分使用来自第二电流源的电流，反之亦然。 每个锁存器的开关部分以比存储器部分更高的电流被偏置，为电路提供低功耗。 提供给切换部分的输出电流优选地是提供给存储器部分的电流的大小的两倍。 取决于时钟频率，开关和存储器部分的电流源的电流比优选在约30％至70％的范围内。

    Radio frequency modulator
    6.
    发明授权
    Radio frequency modulator 有权
    射频调制器

    公开(公告)号：US07136626B2

    公开(公告)日：2006-11-14

    申请号：US10071919

    申请日：2002-02-08

    申请人： Biagio Bisanti ,  Stefano Cipriani ,  Eric Duvivier

    发明人： Biagio Bisanti ,  Stefano Cipriani ,  Eric Duvivier

    IPC分类号： H04B1/02 ,  H04B1/04

    CPC分类号： H03C3/0983 ,  H03C3/0966

    摘要： A transmitter architecture (200) provides for a stable and low noise modulator where the modulation bandwidth is uncorrelated to the TX loop bandwidth. The output signal (228) of the TX loop is demodulated by a demodulator (208) and the demodulated signal is compared by a comparator (206) with the modulating input signal (202). The output of the comparator is then used to adjust a digital pre-emphasis filter (204) which preconditions the modulating input signal (202) in the digital domain. The preconditioning approach of the present invention provides for low noise because the transmitter designer can chose a narrow band for the TX loop which will also filter out the noise coming from the additional synthesizer (226) used to down convert the input signal.

    摘要翻译： 发射机架构（200）提供稳定和低噪声调制器，其中调制带宽与TX环路带宽不相关。 TX环路的输出信号（228）由解调器（208）解调，并且解调信号由比较器（206）与调制输入信号（202）进行比较。 然后比较器的输出用于调整预编码数字域中的调制输入信号（202）的数字预加重滤波器（204）。 本发明的预处理方法提供低噪声，因为发射机设计者可以为TX环路选择窄带，其也将滤除来自用于下变频输入信号的附加合成器（226）的噪声。

    CHARGE PUMP PHASE LOCKED LOOP WITH IMPROVED POWER SUPPLY REJECTION
    7.
    发明申请
    CHARGE PUMP PHASE LOCKED LOOP WITH IMPROVED POWER SUPPLY REJECTION 有权
    充电泵相位锁定环与改进的电源抑制

    公开(公告)号：US20050195002A1

    公开(公告)日：2005-09-08

    申请号：US10793367

    申请日：2004-03-03

    申请人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    发明人： Gianni Puccio ,  Biagio Bisanti ,  Stefano Cipriani

    IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/18

    CPC分类号： H03L7/0895 ,  H03L7/18

    摘要： A phase lock loop circuit (60) has a phase frequency detector (62), a charge pump (64), an active filter (87) and a voltage-controlled oscillator (100). The phase detector generates signals responsive to reference signal FR and VCO output signal FV. A charge pump generates a voltage at the input of a first transmission gate (76) according to the values of the phase detector signals. A predetermined voltage is generated at the input of a second transmission gate (112). When the transmission gates (76, 110) are closed (low impedance) the charge pump may sink or source current to the inverting input of the operational amplifier (86) of the active filter 86 and the predetermined voltage is applied to the non-inverting input. When the transmission gates are open (high impedance state) the inverting input is electrically isolated from the node and the non-inverting output is isolated from the power supply.

    摘要翻译： 锁相环电路（60）具有相位频率检测器（62），电荷泵（64），有源滤波器（87）和压控振荡器（100）。 相位检测器响应于参考信号F SUB和VCO输出信号F OUT产生信号。 电荷泵根据相位检测器信号的值在第一传输门（76）的输入端产生电压。 在第二传输门（112）的输入处产生预定电压。 当传输门（76,110）关闭（低阻抗）时，电荷泵可以将有源滤波器86的运算放大器（86）的反相输入端的电流吸收或输出，并将预定的电压施加到非反相 输入。 当传输门打开（高阻抗状态）时，反相输入与节点电隔离，非反相输出与电源隔离。

    Loop filter architecture
    8.
    发明授权
    Loop filter architecture 有权
    环路滤波器架构

    公开(公告)号：US06600351B2

    公开(公告)日：2003-07-29

    申请号：US10072094

    申请日：2002-02-08

    申请人： Biagio Bisanti ,  Stefano Cipriani ,  Francesco Coppola

    发明人： Biagio Bisanti ,  Stefano Cipriani ,  Francesco Coppola

    IPC分类号： H03L706

    CPC分类号： H03L7/0893

    摘要： A phase-lock loop (PLL) filter architecture includes a first charge pump (508) and a second change pump (510). The second charge pump (510) operates in opposite phase of the first charge pump (508) in order to take away excess charge from the loop filter capacitor(s). By using a second charge pump as described, the PLL filter does not require the use of a large capacitor and can therefore be integrated.

    摘要翻译： 锁相环（PLL）滤波器结构包括第一电荷泵（508）和第二变换泵（510）。 第二电荷泵（510）在第一电荷泵（508）的相反相位操作，以便从环路滤波电容器中夺走过量的电荷。 通过使用如上所述的第二电荷泵，PLL滤波器不需要使用大电容器，因此可以被集成。

    Tuning circuit having electronically trimmed VCO
    10.
    发明授权
    Tuning circuit having electronically trimmed VCO 有权
    调谐电路具有电子调整VCO

    公开(公告)号：US06806781B2

    公开(公告)日：2004-10-19

    申请号：US09815831

    申请日：2001-03-23

    申请人： Biagio Bisanti ,  Francesco Coppola ,  Pascal Guignon

    发明人： Biagio Bisanti ,  Francesco Coppola ,  Pascal Guignon

    IPC分类号： H03L700

    CPC分类号： H03L7/113 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03J5/246 ,  H03L7/099

    摘要： A voltage controlled oscillator (38) includes an LC tank (20) and a capacitor bank (21). LC tank (20) includes an inductor (12) and a varactor (14). The capacitive output of the varactor is controlled by a control voltage &ngr;. To electronically tune the voltage controlled oscillator, a set of capacitors (24) in the capacitor bank (21) are enabled by a digital control signal based on a frequency comparison with a desired frequency. Once the capacitor bank is set, the frequency can be locked at the desired frequency by the phase lock loop.

    摘要翻译： 压控振荡器（38）包括LC箱（20）和电容器组（21）。 LC箱（20）包括电感器（12）和变容二极管（14）。 变容二极管的电容输出由控制电压nu控制。 为了电压调节压控振荡器，电容器组（21）中的一组电容器（24）通过基于与期望频率的频率比较的数字控制信号来实现。 一旦电容器组被置位，频率可以通过锁相环锁定在所需的频率。