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公开(公告)号：US6160507A
公开(公告)日：2000-12-12
申请号：US189073
申请日：1998-11-09
申请人： Pierre Carbou , Pascal Guignon
发明人： Pierre Carbou , Pascal Guignon
IPC分类号： H03K17/041 , H03M1/68 , H03M1/74 , H03M1/66
CPC分类号： H03K17/04106 , H03M1/685 , H03M1/747
摘要： Current bit cell having a current source (P1), a transistor (P6) for detecting the presence of a digital signal bit (Bit) and a plurality of transistors (P2, P5, P7) for detecting at least one command signal (L, Lc) so as to command, on a first output (S1) of the cell, the appearance of a current delivered by the current source (P1) as a function of the digital signal (Bit) applied to the cell and of the at least one command signal (L, Lc), a transistor (P9) for detecting the presence of a bit (Bitz) complementary to the bit of the digital signal (Bit) and a plurality of transistors (P3, P4, P8) for detecting the complement (Lz, Lcz) of the at least one command signal (L, Lc), so as to command on a second output (S2) of the cell the appearance of a current delivered by the current source (P1) which is the complement of the current delivered on the first output (S1), the transistors for detecting the presence of bits and of the at least one command signal, the transistors for detecting the presence of complementary bits and of complementary command signals and the current source being embodied with the aid of field-effect transistors of the same type.
摘要翻译： 具有电流源（P1）的当前位单元，用于检测数字信号位（Bit）的存在的晶体管（P6）和用于检测至少一个指令信号（L，...）的多个晶体管（P2，P5，P7） Lc），以便在单元的第一输出（S1）上命令由电流源（P1）传送的电流的外观作为应用于单元的数字信号（Bit）和至少 一个指令信号（L，Lc），用于检测与数字信号（Bit）的位互补的位（Bitz）的存在的晶体管（P9）和用于检测数字信号的位的多个晶体管（P3，P4，P8） 所述至少一个命令信号（L，Lc）的补码（Lz，Lcz），以便在所述单元的第二输出（S2）上命令出现由当前源（P1）作为补码 在第一输出（S1）上传送的电流，用于检测位的存在和至少一个命令信号的晶体管，用于检测的晶体管 存在互补位和互补指令信号，并且电流源借助于相同类型的场效应晶体管而被实现。
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公开(公告)号：US5610546A
公开(公告)日：1997-03-11
申请号：US164606
申请日：1993-12-09
申请人： Pierre Carbou , Pascal Guignon , Philippe Perney
发明人： Pierre Carbou , Pascal Guignon , Philippe Perney
CPC分类号： H03K5/133 , H03K5/04 , H03K5/1515
摘要： Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.
摘要翻译： 延迟电路包括由连接在两个场效应晶体管（PO，NO）的漏极和源极之间的电流源（I）形成的延迟单元，其栅极彼此连接以构成单元的输入，以及反相器 （INV）根据延迟是否影响待延迟的信号的前沿或后沿，连接到电流源（I）的一个或另一个终端;电容器（C），用于定义延迟时间 （Te）与电源电压成比例并且与由电流源传递的电流（I）成反比，其连接在逆变器（INV）的输入端和地之间，其特征在于，它还包括电路（Ci，Cu ，S1，S3，AMPLO，P1），用于调节由电流源传递的电流，以使其与电路的电源电压成比例。
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公开(公告)号：US06400231B1
公开(公告)日：2002-06-04
申请号：US09642481
申请日：2000-08-18
申请人： Yves Leduc , Pascal Guignon , Pierre Carbou
发明人： Yves Leduc , Pascal Guignon , Pierre Carbou
IPC分类号： H03B500
CPC分类号： H03K3/0307 , H03B5/366 , H03J2200/10
摘要： An oscillator includes a resonator, such as a crystal (12) coupled to first and second capacitor banks (14). The first and second capacitor banks (14) each comprise a plurality of capacitors (16) coupled to the resonator (12) through respective switching devices (18) that may be selectively enabled. The switches (18) are selectively enabled to couple a desired set of said capacitors (16) to said resonator (12). At least one of the switches (18sd) is controlled with a clock signal having a programmable duty cycle from a sigma-delta modulator (20) to enable at least one of said capacitors (16sd) during a first phase of the clock signal and disable that capacitor (16sd) during a second phase of the clock signal.
摘要翻译： 振荡器包括谐振器，例如耦合到第一和第二电容器组（14）的晶体（12）。 第一和第二电容器组（14）各自包括通过可以选择性地使能的各个开关装置（18）耦合到谐振器（12）的多个电容器（16）。 选择性地使开关（18）能够将期望的所述电容器组（16）耦合到所述谐振器（12）。 至少一个开关（18sd）由具有来自Σ-Δ调制器（20）的可编程占空比的时钟信号控制，以在时钟信号的第一阶段期间使能至少一个所述电容器（16sd），并且使能 该电容器（16sd）在时钟信号的第二阶段期间。
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公开(公告)号：US5438291A
公开(公告)日：1995-08-01
申请号：US168707
申请日：1993-12-16
申请人： Pierre Carbou , Pascal Guignon
发明人： Pierre Carbou , Pascal Guignon
CPC分类号： H03K5/082
摘要： Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.
摘要翻译： 受控延迟数字时钟信号发生器，其特征在于它包括从时钟信号（CK）及其互补信号（CK）产生的装置（I5，I6，I7，I8，I9，I10，IT7，IT8，IT9，IT10，C4） CKB）包括至少两个正斜率段和至少两个负斜率段的斜坡信号，所述装置（I1，I2，IT1，IT2，IT3，C2，CET1T2，AMPLI，I3，I4，IT4，IT5，IT6， C3，CET3T4，AMPL2），用于单独控制所述段的斜率的装置，具有用于将斜坡信号（RAMP）转换成方波信号（CKQ）装置（NO0，A0，A1，NO1）的触发电路（AMPLO） 实现由时钟信号（CK）的转换和所述时钟信号的时钟互补时钟信号（CKB）产生的延迟平方时信号（CKQ）的逻辑组合，以获得与斜坡信号相同的延迟的数字时钟信号 有不同坡度的段。
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公开(公告)号：US06806781B2
公开(公告)日：2004-10-19
申请号：US09815831
申请日：2001-03-23
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03J5/246 , H03L7/099
摘要： A voltage controlled oscillator (38) includes an LC tank (20) and a capacitor bank (21). LC tank (20) includes an inductor (12) and a varactor (14). The capacitive output of the varactor is controlled by a control voltage &ngr;. To electronically tune the voltage controlled oscillator, a set of capacitors (24) in the capacitor bank (21) are enabled by a digital control signal based on a frequency comparison with a desired frequency. Once the capacitor bank is set, the frequency can be locked at the desired frequency by the phase lock loop.
摘要翻译： 压控振荡器（38）包括LC箱（20）和电容器组（21）。 LC箱（20）包括电感器（12）和变容二极管（14）。 变容二极管的电容输出由控制电压nu控制。 为了电压调节压控振荡器，电容器组（21）中的一组电容器（24）通过基于与期望频率的频率比较的数字控制信号来实现。 一旦电容器组被置位，频率可以通过锁相环锁定在所需的频率。
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6.发明授权公开(公告)号：US07930572B2
公开(公告)日：2011-04-19
申请号：US10849709
申请日：2004-05-19
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.
摘要翻译： 处理系统包括具有空闲模式节点的处理器（20），用于产生指示处理器处于空闲模式的空闲模式信号和具有用于接收数据保持模式信号的数据保持节点的存储器（22）。 存储器包括用于响应于数据保持模式信号将存储器置于低功率状态的电路。 空闲模式信号驱动数据保留节点，使得当处理器处于空闲模式时，存储器处于低功率状态。
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7.发明申请公开(公告)号：US20050144494A1
公开(公告)日：2005-06-30
申请号：US10849709
申请日：2004-05-19
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.
摘要翻译： 处理系统包括具有空闲模式节点的处理器（20），用于产生指示处理器处于空闲模式的空闲模式信号和具有用于接收数据保持模式信号的数据保持节点的存储器（22）。 存储器包括用于响应于数据保持模式信号将存储器置于低功率状态的电路。 空闲模式信号驱动数据保留节点，使得当处理器处于空闲模式时，存储器处于低功率状态。
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