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公开(公告)号：US20190279588A1
公开(公告)日：2019-09-12
申请号：US16066827
申请日：2017-12-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jiha KIM , Lijun YUAN , Zhichong WANG , Mingfu HAN , Xing YAO , Guangliang SHANG , Seung Woo HAN , Yun Sik IM , Jing LV , Yinglong HUANG , Jung Mok JUN , Haoliang ZHENG
Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.
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12.发明申请公开(公告)号：US20190027079A1
公开(公告)日：2019-01-24
申请号：US15577402
申请日：2017-05-03
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang SHANG , Xing YAO , Mingfu HAN , Seung-Woo HAN , Yun-Sik IM , Jing LV , Yinglong HUANG , Jung-Mok JUN , Xue DONG , Haoliang ZHENG , Lijun YUAN , Zhichong WANG , Ji Ha KIM
Abstract: A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.
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13.发明申请公开(公告)号：US20180108289A1
公开(公告)日：2018-04-19
申请号：US15502983
申请日：2016-05-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Hyunsic CHOI , Mingfu HAN , Xing YAO , Zhichong WANG , Lijun YUAN
CPC classification number: G09G3/2092 , G09G3/20 , G09G2300/0408 , G09G2300/0871 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/02 , G11C19/28
Abstract: The present disclosure relates to a shift register unit and driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: an input module for controlling a level of a first node based on a scan pulse, an output module for controlling a scan pulse output based on the level of the first node, a reset module for resetting the first node and the scan pulse output, and a control module for generating a reset trigger signal, wherein the reset module further resets the first node based on the reset trigger signal. The shift register units can be cascaded to form a gate driving circuit to realize output of multiple scan pulses. By integrating such a gate driving circuit on the array substrate, area of the bezel region of the array substrate can be reduced, thereby facilitating bezel narrowing of a display device. At the same time, due to presence of the control module, the reset module is enabled to reset the first node more stably while normal output of the scan pulse is maintained.
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公开(公告)号：US20250166573A1
公开(公告)日：2025-05-22
申请号：US18290493
申请日：2023-02-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chengyuan LUO , Pan XU , Ying HAN , Donghui ZHAO , Xing ZHANG , Guangshuang LV , Cheng XU , Xing YAO , Dandan ZHOU , Miao LIU
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: A shift register is provided to include: a voltage regulating circuit to adjust voltages at first and second nodes; a light-emitting cascade output circuit to write a second operating voltage from a second power terminal to a light-emitting cascade signal output terminal in response to control of the voltage at the first node, and write a first operating voltage from a first power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the second node; a light-emitting driving output circuit to write a third operating voltage from a third power terminal to a light-emitting control driving signal output terminal in response to control of the voltage at the first node, and write a fifth operating voltage from a fifth power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the second node; and a first anti-leakage circuit to write a fourth operating voltage from a fourth power terminal to a first anti-leakage node in response to control of the voltage at the second node.
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15.发明申请公开(公告)号：US20250166568A1
公开(公告)日：2025-05-22
申请号：US19032469
申请日：2025-01-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang SHANG , Jiangnan LU , Li WANG , Mengyang WEN , Xing YAO , Libin LIU
IPC: G09G3/3233 , G09G3/3266 , G09G3/3275
Abstract: Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.
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Patent Agency Ranking
公开(公告)号：US20250124879A1
公开(公告)日：2025-04-17
申请号：US18687988
申请日：2022-11-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang SHANG , Jianchao ZHU , Jiangnan LU , Yu FENG , Rui XU , Xing YAO
IPC: G09G3/3266
Abstract: Provided are a display panel, a display apparatus and a method for driving the display panel. The display panel includes: multiple gate lines; and multiple shift register units, a target shift register unit of the shift register units includes: a frame trigger selecting circuit and a gate driving circuit; the frame trigger selecting circuit is coupled to a frame trigger input terminal and frame starting signal terminals corresponding to N cascade groups, and outputs, in response to an nth turn-on signal of N turn-on signals corresponding to an nth cascade group, a starting signal input to the frame trigger input terminal to a frame starting signal terminal corresponding to the nth cascade group; 1≤n≤N, and n is an integer; the nth cascade group scans the gate lines coupled thereto line by line after the frame starting signal terminal corresponding thereto receives the starting signal.
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公开(公告)号：US20250095536A1
公开(公告)日：2025-03-20
申请号：US18290015
申请日：2022-11-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Donghui ZHAO , Pan XU , Ying HAN , Xing ZHANG , Chengyuan LUO , Guangshuang LV , Xing YAO , Dandan ZHOU , Miao LIU
IPC: G09G3/20
Abstract: Provided is a pixel drive circuit. The pixel drive circuit includes a plurality of scan drive circuits transmitting gate drive signals to pixels, a plurality of emission drive circuits transmitting emission control signals to the pixels, a plurality of compensation drive circuits transmitting compensation signals to the pixels, and a plurality of reset drive circuits transmitting reset signals to the pixels, which are all cascaded in a pixel column direction. In addition, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit corresponding to the same row of pixels are arranged sequentially along a pixel row direction, the scan drive circuit being disposed farthest away from the pixels. Moreover, among signal lines coupled to the pixel drive circuit, a plurality of signal lines is overlapped with each other, and cutouts are provided at the overlapping portions of the plurality of signal lines.
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公开(公告)号：US20250095524A1
公开(公告)日：2025-03-20
申请号：US18557312
申请日：2022-10-27
IPC: G09G3/00 , G09G3/32 , G09G3/3266 , G09G3/3275
Abstract: A display module includes sub-pixels, data lines, a source driving circuit and a processor. Each sub-pixel includes light-emitting sub-units each including a pixel circuit and at least one light-emitting device. A data line is electrically connected to a sub-pixel. The source driving circuit is electrically connected to the data line. The source driving circuit is configured to output a first or second data signal to the sub-pixel through the data line. The processor is configured to: determine location information of a target sub-pixel; and control, according to the location information, the source driving circuit to output the second data signal to the target sub-pixel, so that a brightness of the target sub-pixel is substantially the same as that of a non-target sub-pixel.
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公开(公告)号：US20250014520A1
公开(公告)日：2025-01-09
申请号：US18272595
申请日：2022-07-28
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU , Luke DING , Cheng XU , Miao LIU , Xing YAO
IPC: G09G3/3266 , G11C19/28
Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.
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公开(公告)号：US20250006134A1
公开(公告)日：2025-01-02
申请号：US18277375
申请日：2022-07-25
Inventor： Xuehuan FENG , Jingbo XU , Xing YAO , Miao LIU
IPC: G09G3/3266 , G11C19/28
Abstract: There is provided a shift register unit, including: a sensing control circuit configured to write an active level signal provided by a sensing active level supply terminal to a first sensing control node in response to an active level signal provided by the random signal input terminal and an active level signal provided by a sensing signal input terminal; a first sensing input circuit configured to write an active level signal to a first pull-up node in response to an active level signal at the first sensing control node and an active level signal provided by a clock control signal input terminal; and a first driving output circuit configured to write a signal provided by a first driving clock signal input terminal to a first driving signal output terminal in response to an active level signal at the first pull-up node. Gate driving circuit and method are further disclosed.
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