公开(公告)号：US20110310035A1

公开(公告)日：2011-12-22

申请号：US13093035

申请日：2011-04-25

Applicant: Sung-Man KIM ,  Beom-Jun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE

Inventor： Sung-Man KIM ,  Beom-Jun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/044

Abstract: A touch sensible display device includes a display panel. The display panel includes a plurality of pixels, a plurality of image data lines transferring image data signals to the plurality of pixels and each positioned between two neighboring pixels, a plurality of image scanning lines transferring image scanning signals to the plurality of pixels, a plurality of first sense data lines transferring first sense data signals and each positioned between two neighboring pixels without the image data line interposed therebetween, and a plurality of first sensing units connected with the plurality of first sense data lines and sensing a touch to the display panel.

Abstract translation: 触敏显示装置包括显示面板。 显示面板包括多个像素，将图像数据信号传送到多个像素并且分别位于两个相邻像素之间的多个图像数据线，将图像扫描信号传送到多个像素的多个图像扫描线，多个像素 第一感测数据线传送第一感测数据信号，并且每个定位在两个相邻像素之间，而不插入图像数据线;以及多个第一感测单元，与多个第一感测数据线连接并感测对显示面板的触摸。

公开(公告)号：US20080067512A1

公开(公告)日：2008-03-20

申请号：US11839125

申请日：2007-08-15

Applicant: Bong-Jun LEE ,  Myung-Koo HUR ,  Sung-Man KIM ,  Hong-Woo LEE

Inventor： Bong-Jun LEE ,  Myung-Koo HUR ,  Sung-Man KIM ,  Hong-Woo LEE

IPC: H01L33/00 ,  G02F1/1343 ,  H01L29/04

CPC classification number: G09G3/3659 ,  G09G3/3614 ,  G09G2300/0443 ,  G09G2300/0452 ,  G09G2310/0251 ,  G09G2310/0281

Abstract: In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period. A pre-charging part pre-charges the pixel electrode to a common voltage that is a reference voltage of the pixel voltage in response to a previous gate pulse during a previous 1H period

Abstract translation: 在阵列基板和显示装置中，栅极线在当前1H周期期间接收栅极脉冲，并且数据线接收每帧具有极性反转的像素电压。 当在本1H时段期间响应于栅极脉冲导通薄膜晶体管时，像素电极在本1H时段期间通过薄膜晶体管接收像素电压。 预充电部件将像素电极预先充电到作为像素电压的参考电压的公共电压，该公共电压响应于之前的1H周期期间的先前的栅极脉冲

公开(公告)号：US20110267326A1

公开(公告)日：2011-11-03

申请号：US12898090

申请日：2010-10-05

Applicant: Sungman KIM ,  Beomjun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE ,  Jae-seung KIM ,  Byung-Su OH

Inventor： Sungman KIM ,  Beomjun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE ,  Jae-seung KIM ,  Byung-Su OH

IPC: G09G5/00 ,  H03K3/00

CPC classification number: G09G3/3677

Abstract: A gate driving circuit includes a plurality of stages which are connected to each other one after another and each stage of the plurality of stages outputs a gate voltage to a corresponding gate line of a plurality of gate lines in response to at least one clock signal. Each stage of the plurality of stages includes; a voltage output part which outputs the gate voltage, an output driving part which drives the voltage output part, a holding part which holds the gate line at an off-voltage, and a discharge part arranged at a first end of the gate line to discharge the gate line to the off-voltage in response to the gate voltage output from the voltage output part,

Abstract translation: 栅极驱动电路包括多个级彼此连接并且多级的每一级响应于至少一个时钟信号而将栅极电压输出到多条栅极线的对应栅极线。 多个阶段的每个阶段包括： 输出栅极电压的电压输出部分，驱动电压输出部分的输出驱动部分，将栅极线保持在截止电压的保持部分和布置在栅极线的第一端以放电的放电部分 所述栅极线响应于从所述电压输出部输出的栅极电压而断开所述截止电压，

公开(公告)号：US20090189677A1

公开(公告)日：2009-07-30

申请号：US12241880

申请日：2008-09-30

Applicant: Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

Inventor： Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

IPC: H03K17/687 ,  G09G5/00

CPC classification number: G09G3/3677

Abstract: A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.

Abstract translation: 门驱动电路包括级级，级联级，每级包括：在水平扫描周期（1H）期间将门电压上拉至时钟信号的上拉部分; 在水平扫描期间（1H）中将进位电压拉入时钟信号的进位部分; 上拉驱动部分连接到与进位部分和上拉部分共同的控制端子（Q-节点），并且从上一级接收先前的进位电压以接通上拉部分和进位 部分; 以及纹波防止部，其基于在所述进位部和所述上拉部的所述Q节点处产生的波纹来防止在前一级的前一Q点产生的纹波。

公开(公告)号：US20070296681A1

公开(公告)日：2007-12-27

申请号：US11760174

申请日：2007-06-08

Applicant: Sung-Man KIM ,  Hong-Woo LEE ,  Byeong Jae AHN ,  Young-Geol SONG ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Kyung-Wook KIM ,  Jin-Suk SEO

Inventor： Sung-Man KIM ,  Hong-Woo LEE ,  Byeong Jae AHN ,  Young-Geol SONG ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Kyung-Wook KIM ,  Jin-Suk SEO

IPC: G09G3/36

CPC classification number: G11C19/184 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/041

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit include a pull-up part and a carry part pull up a present gate signal and a present carry signal, respectively, to a first clock during a first period within one frame. A pull-down part receives a next gate signal to discharge the present gate signal to a source power voltage. A pull-up driving part is connected to control terminals of the carry part and pull-up part (Q-node) to turn the carry part and pull-up part on and off. A floating preventing part prevents an output terminal of the carry part from being floated in response to the first clock during a second period within the one frame.

Abstract translation: 具有栅极驱动电路的栅极驱动电路和显示装置包括上拉部分和进位部分，分别在一帧内的第一时段期间将当前栅极信号和当前进位信号上拉到第一时钟。 下拉部分接收下一个栅极信号，以将当前栅极信号放电到源极电压。 上拉驱动部分连接到进位部分和上拉部分（Q-节点）的控制端子，以使进位部分和上拉部分打开和关闭。 浮动防止部件在一帧内的第二时段期间，响应于第一时钟防止进位部分的输出端子浮起。