公开(公告)号：US20070296681A1

公开(公告)日：2007-12-27

申请号：US11760174

申请日：2007-06-08

申请人： Sung-Man KIM ,  Hong-Woo LEE ,  Byeong Jae AHN ,  Young-Geol SONG ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Kyung-Wook KIM ,  Jin-Suk SEO

发明人： Sung-Man KIM ,  Hong-Woo LEE ,  Byeong Jae AHN ,  Young-Geol SONG ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Kyung-Wook KIM ,  Jin-Suk SEO

IPC分类号： G09G3/36

CPC分类号： G11C19/184 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/041

摘要： A gate driving circuit and a display apparatus having the gate driving circuit include a pull-up part and a carry part pull up a present gate signal and a present carry signal, respectively, to a first clock during a first period within one frame. A pull-down part receives a next gate signal to discharge the present gate signal to a source power voltage. A pull-up driving part is connected to control terminals of the carry part and pull-up part (Q-node) to turn the carry part and pull-up part on and off. A floating preventing part prevents an output terminal of the carry part from being floated in response to the first clock during a second period within the one frame.

摘要翻译： 具有栅极驱动电路的栅极驱动电路和显示装置包括上拉部分和进位部分，分别在一帧内的第一时段期间将当前栅极信号和当前进位信号上拉到第一时钟。 下拉部分接收下一个栅极信号，以将当前栅极信号放电到源极电压。 上拉驱动部分连接到进位部分和上拉部分（Q-节点）的控制端子，以使进位部分和上拉部分打开和关闭。 浮动防止部件在一帧内的第二时段期间，响应于第一时钟防止进位部分的输出端子浮起。

公开(公告)号：US20080050853A1

公开(公告)日：2008-02-28

申请号：US11843194

申请日：2007-08-22

申请人： Jin-Suk SEO ,  Sung-Man KIM ,  Bong-Jun LEE ,  Byeong-Jae AHN ,  Jong Hyuk LEE

发明人： Jin-Suk SEO ,  Sung-Man KIM ,  Bong-Jun LEE ,  Byeong-Jae AHN ,  Jong Hyuk LEE

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F1/13439 ,  H01L27/1214

摘要： In a method of fabricating a display substrate, a photoresist layer pattern is formed on a substrate where a thin film transistor (TFT) is formed, and a transparent conductive layer is formed on the photoresist layer pattern. Then, the transparent conductive layer is patterned by a lift-off method to form a transparent conductive layer pattern while partially removing the photoresist layer pattern.

摘要翻译： 在制造显示基板的方法中，在形成薄膜晶体管（TFT）的基板上形成光致抗蚀剂层图案，并且在光致抗蚀剂层图案上形成透明导电层。 然后，通过剥离法对透明导电层进行图案化以形成透明导电层图案，同时部分去除光致抗蚀剂层图案。

公开(公告)号：US20090189677A1

公开(公告)日：2009-07-30

申请号：US12241880

申请日：2008-09-30

申请人： Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

发明人： Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

IPC分类号： H03K17/687 ,  G09G5/00

CPC分类号： G09G3/3677

摘要： A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.

摘要翻译： 门驱动电路包括级级，级联级，每级包括：在水平扫描周期（1H）期间将门电压上拉至时钟信号的上拉部分; 在水平扫描期间（1H）中将进位电压拉入时钟信号的进位部分; 上拉驱动部分连接到与进位部分和上拉部分共同的控制端子（Q-节点），并且从上一级接收先前的进位电压以接通上拉部分和进位 部分; 以及纹波防止部，其基于在所述进位部和所述上拉部的所述Q节点处产生的波纹来防止在前一级的前一Q点产生的纹波。

公开(公告)号：US20080266477A1

公开(公告)日：2008-10-30

申请号：US11869197

申请日：2007-10-09

申请人： Bong-Jun LEE ,  Kyung-wook KIM ,  Jong-oh KIM ,  Sung-man KIM ,  Hong-woo LEE ,  Hyuk-jin KIM

发明人： Bong-Jun LEE ,  Kyung-wook KIM ,  Jong-oh KIM ,  Sung-man KIM ,  Hong-woo LEE ,  Hyuk-jin KIM

IPC分类号： H03K3/01 ,  G02F1/1368

CPC分类号： G09G3/3677 ,  G02F1/13454 ,  G09G2310/0286 ,  G09G2340/145 ,  G11C19/184

摘要： A gate driving circuit has a first stage which includes: a pull-up driving unit which receives a first carry signal from a second stage and outputs a control signal having first, second, third and fourth voltages to a first node during a preliminary period, a gate active period, a first gate inactive period and a second gate inactive period, respectively; a pull-up unit which receives the control signal and outputs a gate-on signal to a second node during the gate active period; a carry output unit which receives the control signal and outputs a second carry signal to a third stage during the gate active period; and a pull-down unit which receives a gate-off signal and the second carry signal from the second stage and outputs the control signal having the fourth voltage level to the first node during the second gate inactive period.

摘要翻译： 栅极驱动电路具有第一级，其包括：上拉驱动单元，其从初级阶段接收来自第二级的第一进位信号，并将具有第一，第二，第三和第四电压的控制信号输出到第一节点， 栅极有效期，第一栅极无效期和第二栅极非有效期; 上拉单元，其在所述门有效期间内接收所述控制信号并将栅极导通信号输出到第二节点; 进位输出单元，其在所述门有效期间内接收所述控制信号并将第二进位信号输出到第三级; 以及下拉单元，其从第二级接收栅极关闭信号和第二进位信号，并且在第二栅极非活动时段期间将具有第四电压电平的控制信号输出到第一节点。

公开(公告)号：US20090096737A1

公开(公告)日：2009-04-16

申请号：US12128117

申请日：2008-05-28

申请人： Sung-Man KIM ,  Bong-Jun LEE ,  Hong-Woo LEE

发明人： Sung-Man KIM ,  Bong-Jun LEE ,  Hong-Woo LEE

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G2300/0447 ,  G09G2310/0286 ,  G11C19/184

摘要： In a gate driver of a display device, a plurality of first stages each transmit a first gate signal having a first gate-on voltage to first gate lines, and a plurality of second stages each transmit a second gate signal having a second gate-on voltage to second gate lines and output a carry signal corresponding to the second gate signal. Each first stage outputs the first gate-on voltage based on a third gate-on voltage of the carry signal from a previous second stage, and each second stage outputs the second gate-on voltage based on the third gate-on voltage of the carry signal from the previous second stage.

摘要翻译： 在显示装置的栅极驱动器中，多个第一级每个向第一栅极线发送具有第一栅极导通电压的第一栅极信号，并且多个第二级每个发送具有第二栅极导通的第二栅极信号 电压到第二栅极线并输出对应于第二栅极信号的进位信号。 每个第一级基于来自前一第二级的进位信号的第三栅极导通电压输出第一栅极导通电压，并且每个第二级基于进位的第三栅极导通电压输出第二栅极导通电压 来自前一个第二阶段的信号。

公开(公告)号：US20110310035A1

公开(公告)日：2011-12-22

申请号：US13093035

申请日：2011-04-25

申请人： Sung-Man KIM ,  Beom-Jun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE

发明人： Sung-Man KIM ,  Beom-Jun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE

IPC分类号： G06F3/041

CPC分类号： G06F3/0412 ,  G06F3/044

摘要： A touch sensible display device includes a display panel. The display panel includes a plurality of pixels, a plurality of image data lines transferring image data signals to the plurality of pixels and each positioned between two neighboring pixels, a plurality of image scanning lines transferring image scanning signals to the plurality of pixels, a plurality of first sense data lines transferring first sense data signals and each positioned between two neighboring pixels without the image data line interposed therebetween, and a plurality of first sensing units connected with the plurality of first sense data lines and sensing a touch to the display panel.

摘要翻译： 触敏显示装置包括显示面板。 显示面板包括多个像素，将图像数据信号传送到多个像素并且分别位于两个相邻像素之间的多个图像数据线，将图像扫描信号传送到多个像素的多个图像扫描线，多个像素 第一感测数据线传送第一感测数据信号，并且每个定位在两个相邻像素之间，而不插入图像数据线;以及多个第一感测单元，与多个第一感测数据线连接并感测对显示面板的触摸。

公开(公告)号：US20080067512A1

公开(公告)日：2008-03-20

申请号：US11839125

申请日：2007-08-15

申请人： Bong-Jun LEE ,  Myung-Koo HUR ,  Sung-Man KIM ,  Hong-Woo LEE

发明人： Bong-Jun LEE ,  Myung-Koo HUR ,  Sung-Man KIM ,  Hong-Woo LEE

IPC分类号： H01L33/00 ,  G02F1/1343 ,  H01L29/04

CPC分类号： G09G3/3659 ,  G09G3/3614 ,  G09G2300/0443 ,  G09G2300/0452 ,  G09G2310/0251 ,  G09G2310/0281

摘要： In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period. A pre-charging part pre-charges the pixel electrode to a common voltage that is a reference voltage of the pixel voltage in response to a previous gate pulse during a previous 1H period

摘要翻译： 在阵列基板和显示装置中，栅极线在当前1H周期期间接收栅极脉冲，并且数据线接收每帧具有极性反转的像素电压。 当在本1H时段期间响应于栅极脉冲导通薄膜晶体管时，像素电极在本1H时段期间通过薄膜晶体管接收像素电压。 预充电部件将像素电极预先充电到作为像素电压的参考电压的公共电压，该公共电压响应于之前的1H周期期间的先前的栅极脉冲

公开(公告)号：US20130141318A1

公开(公告)日：2013-06-06

申请号：US13485243

申请日：2012-05-31

申请人： Beom-Jun KIM ,  Myung-Koo HUR ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Myung-Sub LEE ,  Gyu-Tae KIM

发明人： Beom-Jun KIM ,  Myung-Koo HUR ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Myung-Sub LEE ,  Gyu-Tae KIM

IPC分类号： G09G3/36 ,  H03K17/693

CPC分类号： G09G3/3688 ,  G09G3/36 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0251 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28 ,  H03K17/693

摘要： A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.

摘要翻译： 提供一种栅极驱动电路，其包括彼此级联的多个级并输出多个栅极信号。 第n（n是自然数）级包括门输出部分，第一节点控制部分和进位部分。 栅极输出部分包括第一晶体管。 第一晶体管响应于控制节点的高电压而将时钟信号的高电压输出到第n栅极信号的高电压。 第一节点控制部分连接到控制节点以控制控制节点的信号，并且包括至少一个具有比第一晶体管的沟道长度更长的沟道的晶体管。 进位部分响应于控制节点的信号将时钟信号的高电压输出到第n进位信号。

公开(公告)号：US20070183218A1

公开(公告)日：2007-08-09

申请号：US11459129

申请日：2006-07-21

申请人： Bong-Jun LEE ,  Chung-Hun HA ,  Jong-Hyuk LEE ,  Shin-Tack KANG ,  Yu-Jin KIM ,  Jin-Suk SEO

发明人： Bong-Jun LEE ,  Chung-Hun HA ,  Jong-Hyuk LEE ,  Shin-Tack KANG ,  Yu-Jin KIM ,  Jin-Suk SEO

IPC分类号： G11C16/04

CPC分类号： G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G11C19/184

摘要： In a gate driving unit and a display apparatus, a first gate driving circuit is connected to a first end of a plurality of gate lines, a second gate driving circuit is connected to a second end of the gate lines, and they are substantially simultaneously turned on. The first and second gate driving circuits apply a first gate signal having a first pre-charging period and a first active period, which is adjacent to the first pre-charging period, to odd-numbered gate lines and apply a second gate signal having a second pre-charging period and a second active period, which is adjacent to the second pre-charging period, to even-numbered gate lines.

摘要翻译： 在栅极驱动单元和显示装置中，第一栅极驱动电路连接到多条栅极线的第一端，第二栅极驱动电路连接到栅极线的第二端，并且基本上同时转动 上。 第一和第二栅极驱动电路将具有与第一预充电周期相邻的第一预充电周期和第一有效周期的第一栅极信号施加到奇数编号的栅极线，并施加具有 与第二预充电周期相邻的第二预充电周期和第二有效周期到偶数栅极线。

公开(公告)号：US20100157234A1

公开(公告)日：2010-06-24

申请号：US12637943

申请日：2009-12-15

申请人： Bong-Jun LEE ,  Kyung-Wook KIM

发明人： Bong-Jun LEE ,  Kyung-Wook KIM

IPC分类号： G02F1/1345 ,  H01L27/088 ,  H01L21/77

CPC分类号： H01L27/124 ,  G02F1/136286

摘要： A display apparatus includes a thin film transistor array panel including a display region and a non-display region, a gate line extending along a first direction, a data line extending along a second direction, substantially perpendicular to the first direction, the data line being insulated from and crossing the gate line, a storage electrode line which receives a common voltage signal, and a first gate driver disposed on the thin film transistor array panel and which supplies at least one of a gate on signal and a gate off signal to the gate line. The storage electrode line includes a first portion extending along the first direction and a second portion extending along the second direction in the non-display region. A width, measured along the second direction, of the first portion is less than a width, measured along the first direction, of the second portion.

摘要翻译： 一种显示装置，具备包括显示区域和非显示区域的薄膜晶体管阵列面板，沿第一方向延伸的栅极线，沿着与第一方向大致垂直的第二方向延伸的数据线，数据线为 绝缘和交叉栅极线，接收公共电压信号的存储电极线和设置在薄膜晶体管阵列面板上的第一栅极驱动器，并且将栅极导通信号和栅极截止信号中的至少一个提供给 门线。 存储电极线包括沿着第一方向延伸的第一部分和在非显示区域中沿第二方向延伸的第二部分。 第一部分沿着第二方向测量的宽度小于第二部分沿着第一方向测量的宽度。