公开(公告)号：US20110175858A1

公开(公告)日：2011-07-21

申请号：US12917018

申请日：2010-11-01

Applicant: Bong-Jun LEE ,  Jong-Hwan LEE ,  Yu-Jin KIM

Inventor： Bong-Jun LEE ,  Jong-Hwan LEE ,  Yu-Jin KIM

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3688 ,  G09G2310/0297 ,  G09G2320/0233

Abstract: In a liquid crystal display apparatus, a first control signal bus line receives a first control signal. A second control signal bus line receives a second control signal that lags behind the first control signal. A de-multiplexer circuit includes a first switching element and a second switching element. The first switching element switches a current path between a first source line and a first data line in response to the first control signal, and the second switching element switches a current path between the first source line and a second data line in response to the second control signal. A pixel part includes a first pixel connected to the first control signal bus line and corresponding to a first color filter, a second pixel connected to the second control signal bus line and corresponding to a second color filter, and a third pixel corresponding to a third color filter, wherein the third pixels are alternately connected to the first control signal bus line and the second control signal bus line.

Abstract translation: 在液晶显示装置中，第一控制信号总线接收第一控制信号。 第二控制信号总线接收滞后第一控制信号的第二控制信号。 解复用器电路包括第一开关元件和第二开关元件。 第一开关元件响应于第一控制信号而在第一源线和第一数据线之间切换电流路径，并且第二开关元件响应于第二开关元件切换第二源线和第二数据线之间的电流路径 控制信号。 像素部分包括连接到第一控制信号总线并对应于第一滤色器的第一像素，连接到第二控制信号总线并对应于第二滤色器的第二像素，以及对应于第三滤色器的第三像素 滤色器，其中第三像素交替地连接到第一控制信号总线和第二控制信号总线。

公开(公告)号：US20080067512A1

公开(公告)日：2008-03-20

申请号：US11839125

申请日：2007-08-15

Applicant: Bong-Jun LEE ,  Myung-Koo HUR ,  Sung-Man KIM ,  Hong-Woo LEE

Inventor： Bong-Jun LEE ,  Myung-Koo HUR ,  Sung-Man KIM ,  Hong-Woo LEE

IPC: H01L33/00 ,  G02F1/1343 ,  H01L29/04

CPC classification number: G09G3/3659 ,  G09G3/3614 ,  G09G2300/0443 ,  G09G2300/0452 ,  G09G2310/0251 ,  G09G2310/0281

Abstract: In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period. A pre-charging part pre-charges the pixel electrode to a common voltage that is a reference voltage of the pixel voltage in response to a previous gate pulse during a previous 1H period

Abstract translation: 在阵列基板和显示装置中，栅极线在当前1H周期期间接收栅极脉冲，并且数据线接收每帧具有极性反转的像素电压。 当在本1H时段期间响应于栅极脉冲导通薄膜晶体管时，像素电极在本1H时段期间通过薄膜晶体管接收像素电压。 预充电部件将像素电极预先充电到作为像素电压的参考电压的公共电压，该公共电压响应于之前的1H周期期间的先前的栅极脉冲

公开(公告)号：US20110267326A1

公开(公告)日：2011-11-03

申请号：US12898090

申请日：2010-10-05

Applicant: Sungman KIM ,  Beomjun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE ,  Jae-seung KIM ,  Byung-Su OH

Inventor： Sungman KIM ,  Beomjun KIM ,  Bong-Jun LEE ,  Hong-Woo LEE ,  Jae-seung KIM ,  Byung-Su OH

IPC: G09G5/00 ,  H03K3/00

CPC classification number: G09G3/3677

Abstract: A gate driving circuit includes a plurality of stages which are connected to each other one after another and each stage of the plurality of stages outputs a gate voltage to a corresponding gate line of a plurality of gate lines in response to at least one clock signal. Each stage of the plurality of stages includes; a voltage output part which outputs the gate voltage, an output driving part which drives the voltage output part, a holding part which holds the gate line at an off-voltage, and a discharge part arranged at a first end of the gate line to discharge the gate line to the off-voltage in response to the gate voltage output from the voltage output part,

Abstract translation: 栅极驱动电路包括多个级彼此连接并且多级的每一级响应于至少一个时钟信号而将栅极电压输出到多条栅极线的对应栅极线。 多个阶段的每个阶段包括： 输出栅极电压的电压输出部分，驱动电压输出部分的输出驱动部分，将栅极线保持在截止电压的保持部分和布置在栅极线的第一端以放电的放电部分 所述栅极线响应于从所述电压输出部输出的栅极电压而断开所述截止电压，

公开(公告)号：US20090189677A1

公开(公告)日：2009-07-30

申请号：US12241880

申请日：2008-09-30

Applicant: Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

Inventor： Hong-Woo LEE ,  Hyeon-Hwan KIM ,  Byeong-Jae AHN ,  Sun-Hyung KIM ,  Sung-Man KIM ,  Bong-Jun LEE

IPC: H03K17/687 ,  G09G5/00

CPC classification number: G09G3/3677

Abstract: A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part.

Abstract translation: 门驱动电路包括级级，级联级，每级包括：在水平扫描周期（1H）期间将门电压上拉至时钟信号的上拉部分; 在水平扫描期间（1H）中将进位电压拉入时钟信号的进位部分; 上拉驱动部分连接到与进位部分和上拉部分共同的控制端子（Q-节点），并且从上一级接收先前的进位电压以接通上拉部分和进位 部分; 以及纹波防止部，其基于在所述进位部和所述上拉部的所述Q节点处产生的波纹来防止在前一级的前一Q点产生的纹波。

公开(公告)号：US20070183218A1

公开(公告)日：2007-08-09

申请号：US11459129

申请日：2006-07-21

Applicant: Bong-Jun LEE ,  Chung-Hun HA ,  Jong-Hyuk LEE ,  Shin-Tack KANG ,  Yu-Jin KIM ,  Jin-Suk SEO

Inventor： Bong-Jun LEE ,  Chung-Hun HA ,  Jong-Hyuk LEE ,  Shin-Tack KANG ,  Yu-Jin KIM ,  Jin-Suk SEO

IPC: G11C16/04

CPC classification number: G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G11C19/184

Abstract: In a gate driving unit and a display apparatus, a first gate driving circuit is connected to a first end of a plurality of gate lines, a second gate driving circuit is connected to a second end of the gate lines, and they are substantially simultaneously turned on. The first and second gate driving circuits apply a first gate signal having a first pre-charging period and a first active period, which is adjacent to the first pre-charging period, to odd-numbered gate lines and apply a second gate signal having a second pre-charging period and a second active period, which is adjacent to the second pre-charging period, to even-numbered gate lines.

Abstract translation: 在栅极驱动单元和显示装置中，第一栅极驱动电路连接到多条栅极线的第一端，第二栅极驱动电路连接到栅极线的第二端，并且基本上同时转动 上。 第一和第二栅极驱动电路将具有与第一预充电周期相邻的第一预充电周期和第一有效周期的第一栅极信号施加到奇数编号的栅极线，并施加具有 与第二预充电周期相邻的第二预充电周期和第二有效周期到偶数栅极线。