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11.发明授权Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture 失效用于光学调制器的硅绝缘体 - 硅薄膜结构和制造方法公开(公告)号：US07177489B2
公开(公告)日：2007-02-13
申请号：US10915299
申请日：2004-08-10
申请人： Thomas Keyser , Cheisan J. Yue , Bradley J. Larsen
发明人： Thomas Keyser , Cheisan J. Yue , Bradley J. Larsen
IPC分类号： G02B1/01 , G02B6/10 , H01L21/302
摘要： The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.
摘要翻译： 本发明提供了可用于形成高频光学调制器的硅基薄膜结构。 本发明的器件形成为具有夹在硅层之间的诸如二氧化硅的薄膜电介质层的分层结构。 硅层具有高自由载流子迁移率。 在本发明的一个方面，可以通过使非晶硅层结晶来提供高迁移率硅层。 在本发明的另一方面，通过使用选择性外延生长和其延伸的横向过度生长，可以提供高迁移率硅层。
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公开(公告)号：US5583380A
公开(公告)日：1996-12-10
申请号：US501503
申请日：1995-07-11
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8238 , H01L23/485 , H01L23/522 , H01L27/092 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76816 , H01L21/76844 , H01L23/485 , H01L2924/0002
摘要： A contact of large dimensions having a stringer strongly adhered to a contact hole's sidewalls. The contact hole is made to have a patterned perimeter having grooves protruding outward. The grooves have a size equal to a minimum contact dimension in at least one direction so as to ensure good step coverage into the groove areas. The grooves serve to anchor the stringer to the contact hole sidewalls by increasing the sidewall's surface area which increases adhesion, distributing stress from the stringer to the groove areas, and providing grooves with good step coverage.
摘要翻译： 具有桁条的大尺寸的接触件牢固地附着在接触孔的侧壁上。 接触孔被制成具有向外突出的凹槽的图案化周边。 凹槽在至少一个方向上具有等于最小接触尺寸的尺寸，以确保凹槽区域的良好的台阶覆盖。 凹槽用于通过增加侧壁的表面积来增加接头孔侧壁，从而增加粘合力，将应力从桁条分布到凹槽区域，并提供具有良好阶梯覆盖的凹槽。
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13.发明申请INTEGRATED CIRCUIT INCLUDING FRONT SIDE AND BACK SIDE ELECTRICAL INTERCONNECTS 审中-公开集成电路，包括正面和背面电气互连公开(公告)号：US20130049215A1
公开(公告)日：2013-02-28
申请号：US13220931
申请日：2011-08-30
申请人： Bradley J. Larsen
发明人： Bradley J. Larsen
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L23/481 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In one example, an integrated circuit includes a silicon on insulator (SOI) substrate including a plurality transistors disposed in a layer of the SOI substrate and a base oxide layer disposed on a first side of the layer. The integrated circuit also may include a first interconnect formed on the first side of the layer, and the first interconnect may electrically connect a first transistor of the plurality of transistors and a second transistor of the plurality of transistors. Additionally, the integrated circuit may include a second interconnect formed on a second side of the layer opposite the first side of the layer, and the second interconnect may electrically connect a third transistor of the plurality of transistors and a fourth transistor of the plurality of transistors.
摘要翻译： 在一个示例中，集成电路包括绝缘体上硅（SOI）衬底，其包括设置在SOI衬底的层中的多个晶体管和设置在该层的第一侧上的基极氧化物层。 集成电路还可以包括形成在层的第一侧上的第一互连，并且第一互连可以电连接多个晶体管中的第一晶体管和多个晶体管中的第二晶体管。 另外，集成电路可以包括形成在与层的第一侧相对的层的第二侧上的第二互连，并且第二互连可以电连接多个晶体管中的第三晶体管和多个晶体管的第四晶体管 。
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公开(公告)号：US20110089331A1
公开(公告)日：2011-04-21
申请号：US12536950
申请日：2009-08-06
IPC分类号： G01T1/24
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
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公开(公告)号：US07378705B2
公开(公告)日：2008-05-27
申请号：US11217829
申请日：2005-09-01
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L27/1203
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.
摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储单元和操作方法，用于在标准CMOS工艺中创建EEPROM存储器单元。 单个多晶硅层与轻掺杂的MOS电容器结合使用。 在EEPROM存储单元中使用的轻掺杂电容器在设计中可以是不对称的。 不对称电容器减少面积。 通过使用多个控制电容器也可以减少由反转引起的进一步的电容变化。 此外，使用多个隧道电容器可提供定制的隧道路径的优点。
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16.发明申请Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie 有权包含“区域高效”身体领带的非平面矽绝缘体设备公开(公告)号：US20090065866A1
公开(公告)日：2009-03-12
申请号：US11853611
申请日：2007-09-11
IPC分类号： H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/78615
摘要： Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.
摘要翻译： 公开了包括“面积效率”的身体搭接的非平面SOI器件。 该器件包括体基片，形成在本体基片的表面上的绝缘体层，以及形成在绝缘体层的表面上的硅体。 硅体优选地包括（i）连接源极区域和漏极区域的非平面沟道，以及（ii）与沟道相邻并且将沟道耦合到电压电位的主体连接。 该器件还包括形成在沟道上的栅极电介质和形成在栅极电介质上的栅极材料。
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17.发明授权Method of forming shallow trench isolation structure in a semiconductor device 有权在半导体器件中形成浅沟槽隔离结构的方法公开(公告)号：US06828212B2
公开(公告)日：2004-12-07
申请号：US10278294
申请日：2002-10-22
IPC分类号： H01L21762
CPC分类号： H01L27/11521 , H01L21/3081 , H01L21/76235
摘要： A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.
摘要翻译： 描述了一种用于制造浅沟槽隔离结构的方法，其中在硅衬底上依次形成底部衬垫氧化物层，中间氮化硅层，中间氧化物层和顶部氮化硅层。 然后进行光刻掩模和各向异性蚀刻以在衬底中形成沟槽。 然后将氧化物材料沉积在顶部氮化硅层的顶部，同时填充沟槽。 然后采用化学机械抛光步骤，通过使用顶部氮化硅层作为阻挡层去除氧化物材料。 然后去除顶部氮化硅层，随后对下面的氧化物层进行各向同性蚀刻。 当中间氮化物层用作自然蚀刻停止物时，氧化物材料被雕刻成期望的形状。 随后去除中间氮化物层和焊盘氧化物层以完成浅沟槽隔离结构的制造。
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公开(公告)号：US5352618A
公开(公告)日：1994-10-04
申请号：US100467
申请日：1993-07-30
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11521 , H01L27/11524 , Y10S148/117 , Y10S148/163 , Y10S438/981
摘要： A method for making submicron dielectric windows for electron tunneling between a floating gate and substrate in a semiconductor EEPROM device. A mask edge overlying an oxide layer on a substrate is undercut a small distance, the area surrounding that small distance is built up with oxide, then a thin layer of oxide is formed in the undercut distance to serve as a tunneling window.
摘要翻译： 一种用于在半导体EEPROM器件中制造浮栅和衬底之间的电子隧穿的亚微米电介质窗的方法。 覆盖衬底上的氧化物层的掩模边缘被切下一小段距离，围绕该小距离的区域由氧化物构成，然后在底切距离处形成薄层氧化物以用作隧道窗口。
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公开(公告)号：US08153985B2
公开(公告)日：2012-04-10
申请号：US12536950
申请日：2009-08-06
IPC分类号： G01T1/16
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
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公开(公告)号：US20110186940A1
公开(公告)日：2011-08-04
申请号：US12699704
申请日：2010-02-03
CPC分类号： G01T3/08 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a stack of interconnect layers deposited on the active semiconductor layer, and a neutron conversion layer deposited on the stack of interconnect layers, wherein the stack of interconnect layers is configured such that at least about 10% of secondary charged particles generated in the neutron conversion layer will have a sufficient ion track length in the active semiconductor layer to generate a detectable charge in the active semiconductor layer. Another semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a neutron conversion layer deposited on the active semiconductor layer, and a stack of interconnect layers deposited on the neutron conversion layer.
摘要翻译： 半导体器件包括衬底，位于衬底上的有源半导体层，沉积在有源半导体层上的互连层堆叠以及沉积在互连层堆叠上的中子转换层，其中互连层堆叠被配置为 在中子转换层中产生的至少约10％的二次带电粒子将在有源半导体层中具有足够的离子轨迹长度以在有源半导体层中产生可检测的电荷。 另一个半导体器件包括衬底，位于衬底上的有源半导体层，沉积在有源半导体层上的中子转换层和沉积在中子转换层上的互连层堆叠。
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