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1.发明授权Silicon-insulator-silicon thin-film structures for optical modulators and methods of manufacture 失效用于光学调制器的硅绝缘体 - 硅薄膜结构和制造方法公开(公告)号：US07177489B2
公开(公告)日：2007-02-13
申请号：US10915299
申请日：2004-08-10
申请人： Thomas Keyser , Cheisan J. Yue , Bradley J. Larsen
发明人： Thomas Keyser , Cheisan J. Yue , Bradley J. Larsen
IPC分类号： G02B1/01 , G02B6/10 , H01L21/302
摘要： The present invention provides silicon based thin-film structures that can be used to form high frequency optical modulators. Devices of the invention are formed as layered structures that have a thin-film dielectric layer, such as silicon dioxide, sandwiched between silicon layers. The silicon layers have high free carrier mobility. In one aspect of the invention a high mobility silicon layer can be provided by crystallizing an amorphous silicon layer. In another aspect of the invention, a high mobility silicon layer can be provided by using selective epitaxial growth and extended lateral overgrowth thereof.
摘要翻译： 本发明提供了可用于形成高频光学调制器的硅基薄膜结构。 本发明的器件形成为具有夹在硅层之间的诸如二氧化硅的薄膜电介质层的分层结构。 硅层具有高自由载流子迁移率。 在本发明的一个方面，可以通过使非晶硅层结晶来提供高迁移率硅层。 在本发明的另一方面，通过使用选择性外延生长和其延伸的横向过度生长，可以提供高迁移率硅层。
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公开(公告)号：US08399845B2
公开(公告)日：2013-03-19
申请号：US13424269
申请日：2012-03-19
IPC分类号： G01T3/00
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
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公开(公告)号：US5583380A
公开(公告)日：1996-12-10
申请号：US501503
申请日：1995-07-11
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8238 , H01L23/485 , H01L23/522 , H01L27/092 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76816 , H01L21/76844 , H01L23/485 , H01L2924/0002
摘要： A contact of large dimensions having a stringer strongly adhered to a contact hole's sidewalls. The contact hole is made to have a patterned perimeter having grooves protruding outward. The grooves have a size equal to a minimum contact dimension in at least one direction so as to ensure good step coverage into the groove areas. The grooves serve to anchor the stringer to the contact hole sidewalls by increasing the sidewall's surface area which increases adhesion, distributing stress from the stringer to the groove areas, and providing grooves with good step coverage.
摘要翻译： 具有桁条的大尺寸的接触件牢固地附着在接触孔的侧壁上。 接触孔被制成具有向外突出的凹槽的图案化周边。 凹槽在至少一个方向上具有等于最小接触尺寸的尺寸，以确保凹槽区域的良好的台阶覆盖。 凹槽用于通过增加侧壁的表面积来增加接头孔侧壁，从而增加粘合力，将应力从桁条分布到凹槽区域，并提供具有良好阶梯覆盖的凹槽。
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公开(公告)号：US20120012957A1
公开(公告)日：2012-01-19
申请号：US12835313
申请日：2010-07-13
IPC分类号： H01L31/115 , H01L31/18
CPC分类号： H01L31/1892 , G01T3/08 , H01L31/115 , Y02E10/50
摘要： A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.
摘要翻译： 制造中子检测器的方法包括：通过至少在衬底上形成氧化层来形成第一晶片，在氧化层上形成有源半导体层，以及在有源半导体层上形成互连层，形成至少一个导电 从所述互连层延伸穿过所述有源半导体层和所述氧化物层，在所述互连层和第二晶片之间形成电路转移键，在形成所述电路转移键之后移除所述第一晶片的所述衬底， 在去除第一晶片的衬底之后，其中所述接合焊盘电连接到所述导电通路，在去除所述第一晶片的衬底之后，在所述氧化物层上沉积阻挡层，以及在所述阻挡层上沉积中子转换层 沉积阻挡层后的层。
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5.再颁专利Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer 有权使用第三多晶硅层集成高性能亚微米CMOS和双聚合非易失性存储器件
公开(公告)号：USRE36777E
公开(公告)日：2000-07-11
申请号：US167919
申请日：1998-10-07
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/34
CPC分类号： H01L27/105
摘要： An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.
摘要翻译： 一种用于集成亚微米CMOS器件和非易失性存储器的装置和方法，其中在半导体衬底上形成热氧化物层和形成在其上的双层多晶硅非易失性存储器件。 通过蚀刻去除热氧化物的一部分，将薄的栅极氧化物和具有亚微米深度的第三多晶硅层沉积到蚀刻区域上。 多晶硅层用作亚微米CMOS器件的栅极。 在这样做时，可以形成亚微米CMOS器件，而不会使器件受到诸如EPROM和EEPROM之类的双重多元非易失性存储器件的形成过程中所需的显着的再氧化，并且实现了单独的器件优化。
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6.发明授权Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer 失效具有均匀厚度的栅极氧化层/电容器介质层的单层多晶硅EEPROM
公开(公告)号：US5440159A
公开(公告)日：1995-08-08
申请号：US357525
申请日：1994-12-16
IPC分类号： H01L27/115 , H01L29/788 , H01L29/68 , H01L29/78
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM transistor fabricated with a single polysilicon layer. An MOS transistor is fabricated with a subsurface electrode region defined by a stripe in a first direction. A layer of thin oxide is arranged in a second stripe, perpendicular to the first stripe and a polysilicon layer, arranged in a third stripe is disposed over the second stripe of thin oxide. An adjoining parallel plate capacitor is formed by a subsurface region of the same conductivity type as the subsurface electrodes in the first stripe. An insulative second plate of thin oxide is joined to the second stripe and a third plate of the capacitor is formed by a polysilicon plate over the oxide plate. Vertical metallization stripes in the first direction may contact with some components, while parallel metal stripes in a second layer in a perpendicular direction may contact with the remaining members. The stripe geometry allows lateral and vertical four-way symmetry for implementation of a large number of memory storage cells on a chip or wafer.
摘要翻译： 用单个多晶硅层制造的EEPROM晶体管。 制造MOS晶体管，其具有在第一方向上由条纹限定的地下电极区域。 薄层氧化物布置在垂直于第一条纹的第二条纹中，并且布置在第三条纹中的多晶硅层设置在第二条薄薄氧化物上。 邻接的平行平板电容器由与第一条纹中的地下电极相同的导电类型的地下区域形成。 薄氧化物的绝缘性第二板与第二条带接合，电容器的第三板由氧化物板上的多晶硅板形成。 在第一方向上的垂直金属化条纹可以与一些部件接触，而在第二层中垂直方向上的平行金属条可以与其余部件接触。 条纹几何形状允许横向和垂直四向对称，用于在芯片或晶片上实现大量存储器存储单元。
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7.发明申请INTEGRATED CIRCUIT INCLUDING FRONT SIDE AND BACK SIDE ELECTRICAL INTERCONNECTS 审中-公开集成电路，包括正面和背面电气互连公开(公告)号：US20130049215A1
公开(公告)日：2013-02-28
申请号：US13220931
申请日：2011-08-30
申请人： Bradley J. Larsen
发明人： Bradley J. Larsen
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L23/481 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In one example, an integrated circuit includes a silicon on insulator (SOI) substrate including a plurality transistors disposed in a layer of the SOI substrate and a base oxide layer disposed on a first side of the layer. The integrated circuit also may include a first interconnect formed on the first side of the layer, and the first interconnect may electrically connect a first transistor of the plurality of transistors and a second transistor of the plurality of transistors. Additionally, the integrated circuit may include a second interconnect formed on a second side of the layer opposite the first side of the layer, and the second interconnect may electrically connect a third transistor of the plurality of transistors and a fourth transistor of the plurality of transistors.
摘要翻译： 在一个示例中，集成电路包括绝缘体上硅（SOI）衬底，其包括设置在SOI衬底的层中的多个晶体管和设置在该层的第一侧上的基极氧化物层。 集成电路还可以包括形成在层的第一侧上的第一互连，并且第一互连可以电连接多个晶体管中的第一晶体管和多个晶体管中的第二晶体管。 另外，集成电路可以包括形成在与层的第一侧相对的层的第二侧上的第二互连，并且第二互连可以电连接多个晶体管中的第三晶体管和多个晶体管的第四晶体管 。
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公开(公告)号：US20110089331A1
公开(公告)日：2011-04-21
申请号：US12536950
申请日：2009-08-06
IPC分类号： G01T1/24
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
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公开(公告)号：US07378705B2
公开(公告)日：2008-05-27
申请号：US11217829
申请日：2005-09-01
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L27/1203
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.
摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储单元和操作方法，用于在标准CMOS工艺中创建EEPROM存储器单元。 单个多晶硅层与轻掺杂的MOS电容器结合使用。 在EEPROM存储单元中使用的轻掺杂电容器在设计中可以是不对称的。 不对称电容器减少面积。 通过使用多个控制电容器也可以减少由反转引起的进一步的电容变化。 此外，使用多个隧道电容器可提供定制的隧道路径的优点。
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公开(公告)号：US08310021B2
公开(公告)日：2012-11-13
申请号：US12835313
申请日：2010-07-13
IPC分类号： H01L31/115
CPC分类号： H01L31/1892 , G01T3/08 , H01L31/115 , Y02E10/50
摘要： A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.
摘要翻译： 制造中子检测器的方法包括：通过至少在衬底上形成氧化层来形成第一晶片，在氧化层上形成有源半导体层，以及在有源半导体层上形成互连层，形成至少一个导电 从所述互连层延伸穿过所述有源半导体层和所述氧化物层，在所述互连层和第二晶片之间形成电路转移键，在形成所述电路转移键之后移除所述第一晶片的所述衬底， 在去除第一晶片的衬底之后，其中所述接合焊盘电连接到所述导电通路，在去除所述第一晶片的衬底之后，在所述氧化物层上沉积阻挡层，以及在所述阻挡层上沉积中子转换层 沉积阻挡层后的层。
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