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    Full match (FM) search algorithm implementation for a network processor
    11.
    发明授权
    Full match (FM) search algorithm implementation for a network processor 失效
    网络处理器的完全匹配（FM）搜索算法实现

    公开(公告)号：US07139753B2

    公开(公告)日：2006-11-21

    申请号：US10650327

    申请日：2003-08-28

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： G06F7/00 ,  H04L12/28

    CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

    摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

    Method and system for network processor scheduling outputs based on multiple calendars
    12.
    发明授权
    Method and system for network processor scheduling outputs based on multiple calendars 失效
    基于多个日历的网络处理器调度输出的方法和系统

    公开(公告)号：US06862292B1

    公开(公告)日：2005-03-01

    申请号：US09548910

    申请日：2000-04-13

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/28

    CPC分类号： H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

    摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。

    Queue manager for a buffer
    20.
    发明授权
    Queue manager for a buffer 失效
    队列管理器为缓冲区

    公开(公告)号：US06557053B1

    公开(公告)日：2003-04-29

    申请号：US09477179

    申请日：2000-01-04

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    IPC分类号： G06F1314

    CPC分类号： G06F13/1673

    摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

    摘要翻译： 提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。 然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个 被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。 优选地，以突发模式将数据写入DRAM并从DRAM读取。