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    High data rate interface with improved link control
    11.
    发明申请
    High data rate interface with improved link control 有权
    高数据速率接口，改善了链路控制

    公开(公告)号：US20050135390A1

    公开(公告)日：2005-06-23

    申请号：US10987123

    申请日：2004-11-12

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: H04L12/28 ,  H04L12/56 ,  H04L12/64 ,  H04L29/06 ,  H04L29/08 ,  H04M1/725

    CPC classification number: H04L65/4069 ,  H04L12/6418 ,  H04L29/06 ,  H04L29/06027 ,  H04L65/1069 ,  H04L65/80 ,  H04L69/12 ,  H04L69/18 ,  H04L69/22 ,  H04L69/24 ,  H04L69/324 ,  H04M1/72527 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Systems and methods for implementing cyclic redundancy checks
    12.
    发明申请
    Systems and methods for implementing cyclic redundancy checks 失效
    用于实现循环冗余校验的系统和方法

    公开(公告)号：US20060168496A1

    公开(公告)日：2006-07-27

    申请号：US11285391

    申请日：2005-11-23

    Applicant: Brian Steele ,  George Wiley

    Inventor： Brian Steele ,  George Wiley

    IPC: H03M13/00

    CPC classification number: H04L1/0045 ,  H03M13/09 ,  H04L1/0061

    Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.

    Abstract translation: 本发明提供了用于实现循环冗余检查以改善链路初始化处理和交换系统错误信息的系统和方法。 在一个方面，提供了包括唯一模式检测器，CRC发生器，CRC初始化器和CRC校验器的循环冗余校验（CRC）校验器。 CRC校验器预先为CRC生成器提供了一个独特的模式。 在接收到通过数字传输链路接收的数据流中的唯一模式之后，CRC检查器继续检查CRC，而不需要排队和存储数据。 在另一方面，提供了一种CRC发生器系统，其有意地破坏CRC值以传输系统错误信息。 CRC发生器系统包括CRC发生器，CRC腐蚀器，误差检测器和误差值发生器。 在一个示例中，数字传输链路是MDDI链路。

    High data rate interface with improved link synchronization
    15.
    发明申请
    High data rate interface with improved link synchronization 有权
    高数据速率接口，改善了链路同步

    公开(公告)号：US20050204057A1

    公开(公告)日：2005-09-15

    申请号：US11008024

    申请日：2004-12-08

    Applicant: Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    Inventor： Jon Anderson ,  Brian Steele ,  George Wiley ,  Shashank Shekhar

    IPC: G06F15/16 ,  H04L12/28 ,  H04L12/40 ,  H04L12/56 ,  H04L29/06 ,  H04M1/725

    CPC classification number: H04L65/1069 ,  H04L12/40071 ,  H04L12/40117 ,  H04L29/06027 ,  H04L65/4069 ,  H04L65/80 ,  H04L69/18 ,  H04L69/22 ,  H04M1/72527 ,  H04W56/00 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/26

    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

    Abstract translation: 一种数据接口，用于通过连接在一起的分组结构通过通信路径在主机和客户端之间传送数字数据，以形成用于传送预先选择的一组数字控制和呈现数据的通信协议。 信号协议被配置为生成，发送和接收形成通信协议的分组的链路控制器使用，并且将数字数据形成为一个或多个类型的数据分组，其中至少一个驻留在主机设备中并耦合到 客户端通过通信路径。 该接口通过短距离“串行”类型数据链路提供了经济高效，低功耗，双向，高速的数据传输机制，可实现微型连接器和薄型柔性电缆，特别适用于 将可穿戴式微型显示器等显示元件连接到便携式计算机和无线通信装置。

    Double data rate serial encoder
    17.
    发明申请
    Double data rate serial encoder 有权
    双数据率串行编码器

    公开(公告)号：US20060179384A1

    公开(公告)日：2006-08-10

    申请号：US11285397

    申请日：2005-11-23

    Applicant: George Wiley ,  Brian Steele ,  Curtis Musfeldt

    Inventor： George Wiley ,  Brian Steele ,  Curtis Musfeldt

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: H04J3/047 ,  H04L25/0264 ,  H04L25/028 ,  H04L25/0292

    Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

    Abstract translation: 提供双数据速率串行编码器。 串行编码器包括具有多个输入的多路复用器，耦合到多路复用器的输入的多个锁存器，使得锁存器能够更新其数据输入的启动器，以及用于选择多路复用器的多个输入之一的计数器 用于输出。 在另一方面，多路复用器在输入转换期间提供无毛刺输出。 多路复用器包括基于由计数器提供的输入选择序列的先验知识而优化的输出选择算法。

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