摘要:
In one embodiment, the method of these teachings includes decomposing the output ripple voltage into its constituent components and utilizing the scale factor necessary for this decomposition to obtain the measure capacitance and ESR for a power supply/converter.
摘要:
A notch filter circuit includes first and second operational amplifiers, each having a capacitor connected from the amplifier output to the input. A third capacitor is connected between the second-amplifier input and the filter circuit input. A first switched-capacitor resistor is connected between the filter circuit input and the first-amplifier input. A second switched-capacitor resistor is connected between the first amplifier output and the second amplifier input. The second-amplifier output is connected to the filter circuit output. A third switched-capacitor resistor is connected between said filter circuit output and said first amplifier input; First and second programmable capacitor arrays are connected respectively in parallel with the third switched-capacitor resistor and in parallel with the first switched-capacitor resistor, so that a change only in the capacitance of the second capacitor array causes a corresponding change in the filter notch depth and a change only in the capacitance of the first capacitor array causes a corresponding change in the filter notch width. The first and second capacitor arrays each have a group of digital programming terminals that may be connected together for making fixed the ratio of the capacitance values of the two arrays. A digitally programmable voltage divider circuit connected in series with the second programmable capacitor array permits the independent programing of notch depth, i.e. without affecting notch width.
摘要:
An amplifier has a first stage employing a pair of differentially connected NMOS amplifier transistors, a second stage composed of a bipolar current mirror circuit and two charge pumps. Each charge pump may be a switching voltage multiplier circuit without the conventional output capacitor. The outputs of the two charge pumps are connected, respectively, to the collector of the current-mirror output transistor and to the commonly connected sources of the NMOS amplifier transistors. Each charge pump serves as both a pulse-voltage energizing source and a load to the amplifier. The amplifier is incorporated with a high-current NMOS transistor in an integrated circuit, wherein one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected. The output (collector) of the differential amplifier is connected to the gate of the NMOS driver transistor so that the load current through the driver transistor is held regulated to a value proportional to the input or reference voltage that is applied to the other input of the differential amplifier. The peak pulse voltage of each charge pump is greater than the DC supply voltage from which the driver transistor and the two charge pumps are energized so that the dynamic range of both the input control voltage and the amplifier output to the gate of the NMOS driver transistor is much greater than the DC supply voltage to the integrated circuit.
摘要:
An improved current pump for use in a Type II phase-locked loop including diodes employed as on-off switches for completing paths for a source current. Apparatus is disclosed for increasing the switching speeds of the diodes by ensuring that diode bias voltages undergo the smallest possible shifts required to switch the diodes.
摘要:
An improved charge pump for use in a phase-locked loop is disclosed in which there is only one current source, and in which all switching components pass current in the same direction. The charge pump may thus be constructed entirely of NPN transistors, which makes it possible to embody it in a single integrated circuit chip. The pump up and pump down currents inherently have the same magnitude and transient characteristics, thus minimizing steady-state errors.
摘要:
Methods for selecting between the two modes (states) of operation, continuous conduction and discontinuous conduction, are disclosed. Systems that are capable of selecting the operating mode and operating in the continuous conduction mode or the discontinuous conduction mode are also disclosed.
摘要:
Methods for selecting between the two modes (states) of operation, continuous conduction and discontinuous conduction, are disclosed. Systems that are capable of selecting the operating mode and operating in the continuous conduction mode or the discontinuous conduction mode are also disclosed.
摘要:
In one embodiment, the digital pulse width modulator of these teachings includes comparators and a number of phases and capable of increasing resolution without increasing clock frequency. In another embodiment, the digital pulse width modulator (DPWM) of these teachings includes equality comparators and a number of phases and increases resolution without increasing clock frequency. A further embodiment of the system of these teachings includes a priority encoded comparator component (in one instance including a number of comparators) comparing duty cycle commands against preset minimums, that embodiment being referred to as a frequency Foldback component. Other embodiments and embodiments of the method of these teachings are also disclosed.
摘要:
Methods and systems, utilizing simplified digital hardware, for measuring parameters needed for control of a system (referred to as a plant) such as a power supply or motor. In one embodiment, the system for measuring the desired parameters includes simplified digital hardware to implement the functionality of transfer function measurement in the plant.
摘要:
A low power magnetic-field detector, of the kind for detecting an ambient magnetic field that is greater than a predetermined field strength, is comprised of a Hail element, a transducer-voltage amplifier, and a zero-crossing comparator, all connected in tandem. A clock and switch are used to chop the energizing current to the Hall element. Alternatively, the amplifier and comparator are also chopped to further reduce power consumption. A clockable flip flop is synchronously enabled for an instant at the end of each period of energizing the Hall element. The comparator output signal is transferred to the flip flop Q output and held there during each period of not energizing the Hall element. A Positive-feedback hysteresis circuit adds a bias voltage to the amplified Hall voltage and is applied to the comparator input to effect comparator hysteresis with memory covering clock-period portions when the Hall element is not energized. The comparator is thus transformed into a Schmitt trigger circuit having hysteresis memory, making it possible to chop the Hall element to substantially reduce the detector power consumption without loosing the hysteresis feature.