公开(公告)号：US10509878B1

公开(公告)日：2019-12-17

申请号：US15688730

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Wen-Hao Liu

IPC: G06F17/50 ,  G06F1/10

Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.

公开(公告)号：US10460066B1

公开(公告)日：2019-10-29

申请号：US15649443

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.

公开(公告)号：US10102328B1

公开(公告)日：2018-10-16

申请号：US15060020

申请日：2016-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Jay Alpert ,  Mehmet Can Yildiz

IPC: G06F17/50

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.