公开(公告)号：US20210066133A1

公开(公告)日：2021-03-04

申请号：US16988892

申请日：2020-08-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI

IPC: H01L21/8234 ,  H01L21/762

Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.

公开(公告)号：US20210005443A1

公开(公告)日：2021-01-07

申请号：US16914541

申请日：2020-06-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Loic GABEN ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI ,  Nicolas POSSEME ,  Shay REBOH

IPC: H01L21/02 ,  H01L21/8238 ,  H01L21/3105

Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.

公开(公告)号：US20240341201A1

公开(公告)日：2024-10-10

申请号：US18304531

申请日：2023-04-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Cyrille LE ROYER ,  Fabrice NEMOUCHI ,  Nicolas POSSEME ,  Sébastien KERDILES ,  François LEFLOCH

IPC: H10N60/01 ,  H10N60/10

CPC classification number: H10N60/0912 ,  H10N60/128

Abstract: A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of:



making, over a semiconductor layer, a protective dielectric portion arranged over a first region of the semiconductor layer;
implanting dopants in second regions adjacent to the first region;
depositing a protective dielectric layer covering the protective dielectric portion and the second regions;
exposing the protective dielectric layer to a laser pulse;




and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.

公开(公告)号：US20230186136A1

公开(公告)日：2023-06-15

申请号：US18057435

申请日：2022-11-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Cyrille LE ROYER ,  François LEFLOCH ,  Fabrice NEMOUCHI ,  Nicolas POSSEME

IPC: G06N10/40 ,  H10N60/12

CPC classification number: G06N10/40 ,  H10N60/12

Abstract: A method for producing a quantum device comprising forming a supraconductive layer, forming a mask on the supraconductive layer, the mask comprising masking patterns and at least two openings alternately in a direction, the at least two openings being separated from one another by a separation distance pi (i=1 . . . n), and further each having a width di (i=1 . . . n+1), such as the separation distance pi and a width di are less than a coherence length of a Cooper pair in said supraconductive material, and modifying, through the at least two openings, of the exposed portions of the supraconductive layer, so as to form at least two barriers of width di separating the supraconductive regions.

公开(公告)号：US20220173229A1

公开(公告)日：2022-06-02

申请号：US17456400

申请日：2021-11-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Louis HUTIN ,  Cyrille LE ROYER ,  François LEFLOCH ,  Fabrice NEMOUCHI ,  Maud VINET

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/43

Abstract: A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.

公开(公告)号：US20200274321A1

公开(公告)日：2020-08-27

申请号：US16472136

申请日：2017-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Elodie GHEGIN ,  Christophe JANY ,  Fabrice NEMOUCHI ,  Philippe RODRIGUEZ ,  Bertrand SZELAG

IPC: H01S5/042 ,  H01S5/02 ,  H01S5/183 ,  H01S5/343

Abstract: A process for producing a component includes a structure made of III-V material(s) on the surface of a substrate, the structure comprising at least one upper contact level defined on the surface of a first III-V material and a lower contact level defined on the surface of a second III-V material, comprising: successive operations of encapsulation of the structure with at least one dielectric; making primary apertures in a dielectric for the two contacts; making secondary apertures in a dielectric for the two contacts; at least partial filling of the apertures with at least one metallic material so as to produce upper contact bottom metallization and at least one upper contact pad in contact with the metallization for each of said contacts. A component produced by the process is also provided. The component may be a laser diode.