公开(公告)号：US20230201871A1

公开(公告)日：2023-06-29

申请号：US18068759

申请日：2022-12-20

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Pierre BRIANCEAU ,  Nicolas POSSEME ,  Elisa VERMANDE

IPC: B05D3/14 ,  B05D1/00

CPC classification number: B05D3/145 ,  B05D1/62 ,  B05D2203/30

Abstract: A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, and before or after the provision of the structure, a deposition in the reaction chamber of a layer based on a material of chemical formula CxHyFz, at least x and z being non-zero. The method further includes a treatment, in the presence of the structure, of the layer based on a material of chemical formula CxHyFz by an activation plasma based on at least one from among oxygen and nitrogen. The treatment by the activation plasma is configured to consume at least partially the layer based on the material of chemical formula CxHyFz so as to activate the exposed layer of the structure.

公开(公告)号：US20220271149A1

公开(公告)日：2022-08-25

申请号：US17652315

申请日：2022-02-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Valentin BACQUIE

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/786

Abstract: A method is provided for etching a dielectric layer covering a top and a flank of a three-dimensional structure, the method including: a first etching of the dielectric layer, including: a first fluorine-based compound and oxygen, the first etching being performed to: form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and the second etchings being repeated until removing the dielectric layer located on the flank of the structure, and before deposition of the dielectric layer, a formation of an intermediate protective layer between the top and the dielectric layer.

公开(公告)号：US20220270888A1

公开(公告)日：2022-08-25

申请号：US17652312

申请日：2022-02-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Valentin BACQUIE

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/66

Abstract: A method for etching a dielectric layer covering a top and a flank of a three-dimensional structure, this method including a first etching of the dielectric layer, including a first fluorine based compound, a second compound taken from SiwCl(2w+2) and SiwF(2w+2), oxygen, this first etching being carried out to form a first protective layer on the top and form a second protective layer on the dielectric layer, a second etching configured to remove the second protective layer while retaining a portion of the first protective layer, the first and second etchings being repeated until removing the dielectric layer located on the flank of the structure. The second etching can be carried out by hydrogen-based plasma.

公开(公告)号：US20220172093A1

公开(公告)日：2022-06-02

申请号：US17456388

申请日：2021-11-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Louis HUTIN ,  Cyrille LE ROYER ,  François LEFLOCH ,  Fabrice NEMOUCHI ,  Maud VINET

IPC: G06N10/00 ,  H01L39/22 ,  H01L39/24 ,  H01L29/66

Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.

公开(公告)号：US20190267233A1

公开(公告)日：2019-08-29

申请号：US16343774

申请日：2017-10-20

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Guillaume CLAVEAU ,  Maxime ARGOUD ,  Nicolas POSSEME ,  Raluca TIRON

IPC: H01L21/027 ,  G03F7/00 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

Abstract: A method for forming a functionalised assembly guide intended for the self-assembly of a block copolymer by graphoepitaxy, includes forming on the surface of a substrate a neutralisation layer made of a first material having a first neutral chemical affinity with regard to the block copolymer; forming on the neutralisation layer a first mask including at least one recess; depositing on the neutralisation layer a second material having a second preferential chemical affinity for one of the copolymer blocks, in such a way as to fill the at least one recess of the first mask; and selectively etching the first mask relative to the first and second materials, thereby forming at least one guide pattern made of the second material arranged on the neutralisation layer.

公开(公告)号：US20170372967A1

公开(公告)日：2017-12-28

申请号：US15625852

申请日：2017-06-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Laurent BRUNET ,  Nicolas POSSEME

IPC: H01L21/8234 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/8234 ,  H01L21/56 ,  H01L21/8221 ,  H01L24/83 ,  H01L27/0688 ,  H01L2224/8303 ,  H01L2924/1306

Abstract: A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.

公开(公告)号：US20170372904A1

公开(公告)日：2017-12-28

申请号：US15538564

申请日：2015-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stephan LANDIS ,  Nicolas POSSEME ,  Sebastien BARNOLA ,  Thibaut DAVID ,  Lamia NOURI

IPC: H01L21/266 ,  C23C14/04 ,  C23C14/48 ,  H01L21/306 ,  H01L21/3065 ,  H01L33/22 ,  G03F7/00 ,  H01L31/0392 ,  H01L31/18 ,  H01L33/00 ,  B81C1/00

CPC classification number: H01L21/266 ,  B81C1/00103 ,  B81C1/0046 ,  B81C1/00587 ,  B81C2201/0136 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/042 ,  C23C14/48 ,  G03F7/0002 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L31/02363 ,  H01L31/0392 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/20 ,  H01L33/22 ,  Y02E10/50

Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patterns.

公开(公告)号：US20170207320A1

公开(公告)日：2017-07-20

申请号：US15408793

申请日：2017-01-18

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Christian ARVET ,  Nicolas POSSEME

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66636 ,  H01L21/02238 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L29/66772

Abstract: A method for manufacturing a transistor is provided, the transistor including a gate disposed above an underlying layer of a semiconductor material, the gate including at least one first flank and at least one second flank, and a gate foot disposed under the gate in the underlying layer and protruding relative to a peripheral portion of the underlying layer, the peripheral portion surrounding the gate foot; and the method including forming a selectivity layer obtained from an original layer and disposed only above the peripheral portion of the underlying layer, and selective etching, with respect to the selectivity layer, of the material of the original layer so as to etch the gate foot.

公开(公告)号：US20160254165A1

公开(公告)日：2016-09-01

申请号：US15030459

申请日：2014-11-19

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME

IPC: H01L21/311 ,  H01L21/266 ,  H01L21/265

CPC classification number: H01L21/31144 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31138 ,  H01L21/823814 ,  H01L21/823828

Abstract: The method includes the steps of: a) providing a silicon substrate including a first portion covered by the mask made from a carbonaceous material and a second doped portion, the mask including, at the surface, a surface layer including implanted ionic species and an underlying layer free of implanted ionic species, b) exposing the surface layer and the second portion to a SiCl4 and Cl2 plasma so as to deposit a silicon chloride SiClx layer on the second portion and etch the surface layer, c) etching the underlying layer so as to expose the first portion, and d) etching the silicon chloride SiClx layer so as to expose the second portion.

Abstract translation: 该方法包括以下步骤：a）提供硅衬底，其包括被由碳质材料制成的掩模覆盖的第一部分和第二掺杂部分，所述掩模在表面包括包括注入离子物质的表面层和底层 层），b）将表面层和第二部分暴露于SiCl 4和Cl 2等离子体，以便在第二部分上沉积氯化硅SiClx层并蚀刻表面层，c）蚀刻下面的层，以便 暴露第一部分，以及d）蚀刻氯化硅SiClx层以露出第二部分。

公开(公告)号：US20240341201A1

公开(公告)日：2024-10-10

申请号：US18304531

申请日：2023-04-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Cyrille LE ROYER ,  Fabrice NEMOUCHI ,  Nicolas POSSEME ,  Sébastien KERDILES ,  François LEFLOCH

IPC: H10N60/01 ,  H10N60/10

CPC classification number: H10N60/0912 ,  H10N60/128

Abstract: A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of:



making, over a semiconductor layer, a protective dielectric portion arranged over a first region of the semiconductor layer;
implanting dopants in second regions adjacent to the first region;
depositing a protective dielectric layer covering the protective dielectric portion and the second regions;
exposing the protective dielectric layer to a laser pulse;




and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.