公开(公告)号：US10997352B1

公开(公告)日：2021-05-04

申请号：US16416008

申请日：2019-05-17

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Mehmet Can Yildiz ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Zhuo Li ,  Derong Liu

IPC: G06F30/394 ,  G06F30/18 ,  G06F30/327

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

公开(公告)号：US10460064B1

公开(公告)日：2019-10-29

申请号：US15649415

申请日：2017-07-13

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Wen-Hao Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.

公开(公告)号：US10289792B1

公开(公告)日：2019-05-14

申请号：US15636410

申请日：2017-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Wing-Kai Chow ,  Wen-Hao Liu ,  Gracieli Posser ,  Mehmet Can Yildiz

IPC: G06F17/50

Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.