公开(公告)号：US11734485B1

公开(公告)日：2023-08-22

申请号：US17314932

申请日：2021-05-07

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Derong Liu ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F30/398

Abstract: Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

公开(公告)号：US11675955B1

公开(公告)日：2023-06-13

申请号：US17303052

申请日：2021-05-19

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/398

Abstract: Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

公开(公告)号：US11080457B1

公开(公告)日：2021-08-03

申请号：US16823093

申请日：2020-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Yi-Xiao Ding ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/31 ,  G06F30/327 ,  G06F119/12

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

公开(公告)号：US11132489B1

公开(公告)日：2021-09-28

申请号：US16805155

申请日：2020-02-28

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Yi-Xiao Ding ,  Zhuo Li ,  Mehmet Can Yildiz

IPC: G06F30/3947 ,  G06F30/398 ,  G06F30/392

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

公开(公告)号：US10289795B1

公开(公告)日：2019-05-14

申请号：US15683659

申请日：2017-08-22

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Thomas Andrew Newton ,  Derong Liu ,  Mehmet Can Yildiz ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.

公开(公告)号：US10997352B1

公开(公告)日：2021-05-04

申请号：US16416008

申请日：2019-05-17

Applicant: Cadence Design Systems, Inc.

Inventor： Gracieli Posser ,  Mehmet Can Yildiz ,  Wen-Hao Liu ,  Wing-Kai Chow ,  Zhuo Li ,  Derong Liu

IPC: G06F30/394 ,  G06F30/18 ,  G06F30/327

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

公开(公告)号：US09785738B1

公开(公告)日：2017-10-10

申请号：US14972809

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Charles Jay Alpert ,  Zhuo Li ,  Wing Kai Chow ,  Wen-Hao Liu ,  Derong Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.