公开(公告)号：US08319783B1

公开(公告)日：2012-11-27

申请号：US12340493

申请日：2008-12-19

申请人： David Kirk McAllister ,  Steven E. Molnar ,  Peter B. Holmqvist ,  Jerome F. Duluk, Jr. ,  Cass W. Everitt ,  Emmett M. Kilgariff ,  Patrick R. Brown ,  Christian Johannes Amsinck

发明人： David Kirk McAllister ,  Steven E. Molnar ,  Peter B. Holmqvist ,  Jerome F. Duluk, Jr. ,  Cass W. Everitt ,  Emmett M. Kilgariff ,  Patrick R. Brown ,  Christian Johannes Amsinck

IPC分类号： G06T1/60 ,  G09G5/39 ,  G09G5/36 ,  G09G5/37

CPC分类号： G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/122

摘要： A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each portion of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.

摘要翻译： 执行零带宽清除的系统和方法在执行清除和后续读取操作时减少图形处理器的外部存储器访问。 一组清晰的值存储在图形处理器中。 可以使用零带宽清除命令来配置颜色或z缓冲器的每个部分，以引用清除值而不写入外部存储器。 当执行读取访问时，清除值被提供给请求者而不访问外部存储器。

公开(公告)号：US08085272B1

公开(公告)日：2011-12-27

申请号：US11556657

申请日：2006-11-03

申请人： Steven E. Molnar ,  Cass W. Everitt ,  Roger L. Allen ,  Gary M. Tarolli ,  John M. Danskin ,  Adam Clark Weitkemper ,  Mark J. French

发明人： Steven E. Molnar ,  Cass W. Everitt ,  Roger L. Allen ,  Gary M. Tarolli ,  John M. Danskin ,  Adam Clark Weitkemper ,  Mark J. French

IPC分类号： G06F15/80

CPC分类号： G06T15/005

摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.

摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记 基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性 公共输入流。 每个片段流被独立地处理并对应于其中一个ROP请求流。

公开(公告)号：US07999820B1

公开(公告)日：2011-08-16

申请号：US11953812

申请日：2007-12-10

申请人： Adam Clark Weitkemper ,  Steven E. Molnar ,  Mark J. French ,  Cass W. Everitt

发明人： Adam Clark Weitkemper ,  Steven E. Molnar ,  Mark J. French ,  Cass W. Everitt

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F12/06

CPC分类号： G06F12/0223 ,  G06F12/10 ,  G09G5/39 ,  G09G2360/122

摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint on a display screen to a group of contiguous physical memory locations in a memory system, determining an anchor physical memory address from a first transaction associated with the footprint, wherein the anchor physical memory address corresponds to an anchor in the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits (LSBs) associated with the second transaction, and combining the anchor physical memory address with the set of LSBs associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

摘要翻译： 公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。 本发明的一个实施例提出了一种方法，其包括将显示屏幕上的占位面积映射到存储器系统中的一组连续物理存储器位置，从与所述覆盖区相关联的第一事务确定锚物理存储器地址，其中， 锚物理存储器地址对应于连续物理存储器位置组中的锚点，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位（LSB），以及组合锚物理 存储器地址与与第二事务相关联的一组LSB产生用于第二事务的第二物理存储器地址，从而避免第二次完全地址转换。

公开(公告)号：US07944452B1

公开(公告)日：2011-05-17

申请号：US11552093

申请日：2006-10-23

申请人： Adam Clark Wietkemper ,  Steven E. Molnar ,  Mark J. French ,  Cass W. Everitt

发明人： Adam Clark Wietkemper ,  Steven E. Molnar ,  Mark J. French ,  Cass W. Everitt

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F12/06

CPC分类号： G06F12/10 ,  G06F12/0223 ,  G09G5/39

摘要： Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to a group of contiguous physical memory locations in a memory system, determining a first physical memory address for a first transaction associated with the footprint, wherein the first physical memory address is within the group of contiguous physical memory locations, determining a second transaction that is also associated with the footprint, determining a set of least significant bits associated with the second transaction, and combining a portion of the first physical memory address with the set of least significant bits associated with the second transaction to generate a second physical memory address for the second transaction, thereby avoiding a second full address translation.

摘要翻译： 公开了用于重新使用图形系统中的存储器地址的方法和系统，从而可以减少地址转换硬件的实例。 本发明的一个实施例提出了一种方法，其包括将屏幕空间中的占位面积映射到存储器系统中的一组连续的物理存储器位置，确定与所述覆盖区相关联的第一事务的第一物理存储器地址，其中所述第一 物理存储器地址在连续的物理存储器位置组内，确定也与占用空间相关联的第二事务，确定与第二事务相关联的一组最低有效位，以及将第一物理存储器地址的一部分与 与第二事务相关联的一组最低有效位以产生用于第二事务的第二物理存储器地址，从而避免第二完整地址转换。

公开(公告)号：US20100002000A1

公开(公告)日：2010-01-07

申请号：US12167998

申请日：2008-07-03

申请人： Cass W. Everitt ,  Steven E. Molnar

发明人： Cass W. Everitt ,  Steven E. Molnar

IPC分类号： G06T15/50

CPC分类号： G06T15/503 ,  G06T11/40 ,  G06T2200/28 ,  G06T2210/52

摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.

公开(公告)号：US08692844B1

公开(公告)日：2014-04-08

申请号：US09675099

申请日：2000-09-28

申请人： Steven E. Molnar ,  David B. Kirk ,  John Stephen Montrym ,  Douglas A. Voorhies

发明人： Steven E. Molnar ,  David B. Kirk ,  John Stephen Montrym ,  Douglas A. Voorhies

IPC分类号： G09G5/00 ,  G06T11/20 ,  G06T11/40 ,  G09G5/14

CPC分类号： G06T11/203 ,  G06T11/40 ,  G09G5/14

摘要： A method and system are disclosed for antialiased rendering a plurality of pixels in a computer system. The method and system comprise providing a fixed storage area and providing a plurality of sequential format levels for the plurality of pixels within the fixed storage area. The plurality of format levels represent pixels with varying degrees of complexity in subpixel geometry visible within the pixel. A system and method in accordance with the present invention provides at least the following format levels: one-fragment format, used when one surface fully covers a pixel; two-fragment format, used when two surfaces together cover a pixel; and multisample format, used when three or more surfaces cover a pixel. The method and system further comprise storing the plurality of pixels at a lowest appropriate format level within the fixed storage area, so that a minimum amount of data is transferred to and from the fixed storage area. The method and system further comprise procedures for converting pixels from one format level to take into account newly rendered pixel fragments. All formats represent depth values in a consistent manner so that fragments rendered during later rendering passes match depth values resulting from rendering the same primitive in earlier passes. Thus, the invention enables high-quality antialiasing with minimal data transferred to and from the fixed storage area, while supporting multi-pass rendering.

摘要翻译： 公开了一种用于在计算机系统中抗锯齿渲染多个像素的方法和系统。 所述方法和系统包括提供固定存储区域并为固定存储区域内的多个像素提供多个顺序格式级别。 多个格式级别表示在像素内可见的子像素几何形状具有不同程度的复杂度的像素。 根据本发明的系统和方法至少提供以下格式级别：当一个表面完全覆盖像素时使用的单片段格式; 两片段格式，当两个表面一起覆盖一个像素时使用; 和多重采样格式，当三个或更多个表面覆盖像素时使用。 所述方法和系统还包括将所述多个像素存储在所述固定存储区域内的最低适当格式级别，使得最小量的数据被传送到所述固定存储区域和从所述固定存储区域传送。 该方法和系统还包括用于从一个格式级别转换像素以考虑新渲染的像素片段的过程。 所有格式都以一致的方式表示深度值，以便在后续渲染过程中渲染的片段匹配在较早的通过中渲染相同原语而产生的深度值。 因此，本发明能够以最小的数据传输到固定存储区域和从固定存储区域传输高质量的抗锯齿，同时支持多遍渲染。

公开(公告)号：US08508544B1

公开(公告)日：2013-08-13

申请号：US11593368

申请日：2006-11-02

申请人： Steven E. Molnar ,  Franklin C. Crow

发明人： Steven E. Molnar ,  Franklin C. Crow

IPC分类号： G06T9/00

CPC分类号： G06T9/00

摘要： A method and system for selective enablement of tile compression. The method includes receiving a graphics primitive for processing in a set-up unit of a graphics processor and determining a primitive characteristic that indicates a probability of whether a final compression of a tile related to the primitive will be retained. Compression for the tile related to the primitive is allowed when the characteristic indicates the final compression will be retained. Compression for the tile related to the primitive is disallowed in the characteristic indicates the final compression will not be retained.

摘要翻译： 一种用于选择性地实现瓦片压缩的方法和系统。 该方法包括接收用于在图形处理器的设置单元中进行处理的图形基元，并且确定指示是否将保留与该图元相关的瓦片的最终压缩的概率的原始特性。 当特征指示最终压缩将被保留时，允许与原语相关的瓦片的压缩。 对于与原语相关的瓦片的压缩不允许在特征中表示最终的压缩将不会被保留。

公开(公告)号：US08427495B1

公开(公告)日：2013-04-23

申请号：US11954722

申请日：2007-12-12

申请人： John H. Edmondson ,  Robert A. Alfieri ,  Michael F. Harris ,  Steven E. Molnar

发明人： John H. Edmondson ,  Robert A. Alfieri ,  Michael F. Harris ,  Steven E. Molnar

IPC分类号： G06F12/02

CPC分类号： G06T1/60 ,  H04N19/423

摘要： Write operations to a unit of compressible memory, known as a compression tile, are examined to see if data blocks to be written completely cover a single compression tile. If the data blocks completely cover a single compression tile, the write operations are coalesced into a single write operation and the single compression tile is overwritten with the data blocks. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.

摘要翻译： 对可压缩存储器（称为压缩片）的单位进行写操作，以查看要写入的数据块是否完全覆盖单个压缩片。 如果数据块完全覆盖单个压缩块，则写入操作合并为单个写入操作，并且单个压缩块被数据块覆盖。 将多个写入操作合并为单个写入操作会提高性能，因为它避免了否则需要的读取 - 修改 - 写入操作。

公开(公告)号：US20120026171A1

公开(公告)日：2012-02-02

申请号：US13269462

申请日：2011-10-07

申请人： John M. Danskin ,  John S. Montrym ,  John Erik Lindholm ,  Steven E. Molnar ,  Mark French

发明人： John M. Danskin ,  John S. Montrym ,  John Erik Lindholm ,  Steven E. Molnar ,  Mark French

IPC分类号： G06T15/50

CPC分类号： G06T15/005 ,  G06T2210/52 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/06 ,  G09G2360/122

摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.

摘要翻译： 用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。 耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

公开(公告)号：US20110090220A1

公开(公告)日：2011-04-21

申请号：US12580017

申请日：2009-10-15

申请人： Steven E. Molnar ,  Emmett M. Kilgariff ,  Johnny S. Rhoades ,  Timothy John Purcell ,  Sean J. Treichler ,  Ziyad S. Hakura ,  Franklin C. Crow ,  James C. Bowman

发明人： Steven E. Molnar ,  Emmett M. Kilgariff ,  Johnny S. Rhoades ,  Timothy John Purcell ,  Sean J. Treichler ,  Ziyad S. Hakura ,  Franklin C. Crow ,  James C. Bowman

IPC分类号： G06F15/80 ,  G06T15/00

CPC分类号： G06T15/005 ,  G06T2210/52

摘要： One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

摘要翻译： 本发明的一个实施例提出了一种用于在保持API原语排序的同时并行渲染图形基元的技术。 多个独立的几何单元在不同的图形基元上同时执行几何处理。 原始分配方案以每个时钟的多个基元的速率同时向多个光栅化器提供原语，同时保持每个像素的原始排序。 多个独立的光栅化器单元在一个或多个图形基元上同时执行光栅化，使得能够每个系统时钟渲染多个基元。