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公开(公告)号：US20240169924A1
公开(公告)日：2024-05-23
申请号：US17778916
申请日：2021-06-18
发明人： Guangliang SHANG , Libin LIU , Mengyang WEN , Jiangnan LU , Li WANG , Long HAN
IPC分类号： G09G3/3266 , G09G3/3233 , H10K59/131
CPC分类号： G09G3/3266 , G09G3/3233 , H10K59/131 , G09G2300/0426 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/0286 , G09G2310/08 , G09G2320/0233 , G09G2320/0257 , G09G2330/021
摘要： The embodiments of the present disclosure provides a display substrate, including: an active region and a peripheral region, the active region is provided therein with a plurality of pixel units arranged in an array, all the pixel units are divided into n pixel unit groups, the peripheral region is provided therein with a driver block including a first gate drive circuit having n+x first signal output terminals configured to sequentially output first gate drive signals in an active level and the first gate line provided for an ith pixel unit group is electrically connected to a (i+x)th first signal output terminal, and the reset signal line provided for the ith pixel unit group is electrically connected to an ith first signal output terminal, with i being a positive integer and i≤n.
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公开(公告)号：US20240144885A1
公开(公告)日：2024-05-02
申请号：US17771016
申请日：2021-05-27
发明人： Long HAN , Guangliang SHANG , Libin LIU
IPC分类号： G09G3/3266 , G11C19/28
CPC分类号： G09G3/3266 , G11C19/28 , G09G2310/0286 , G09G2310/08 , G09G2330/021
摘要： Disclosed is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, the gate drive circuit includes a plurality of cascaded shift register units, and a shift register unit is connected with at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected with a first group of clock signal lines, and the second output circuit is connected with the first group of clock signal lines and a second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit.
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公开(公告)号：US20240105119A1
公开(公告)日：2024-03-28
申请号：US17637815
申请日：2021-04-23
发明人： Libin LIU , Li WANG , Guangliang SHANG , Yu FENG , Long HAN , Baoyun WU , Shiming SHI
IPC分类号： G09G3/3233
CPC分类号： G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2320/0233 , G09G2340/0435
摘要： A pixel circuit, a driving method therefor and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a leak-proof sub-circuit, a storage sub-circuit and a light-emitting element. The reset sub-circuit is configured to reset a fourth node under control of a signal of a light-emitting control signal terminal and reset a fifth node under control of a signal of a reset control signal terminal. The compensation sub-circuit is configured to compensate a threshold voltage of the driving sub-circuit to the fifth node under the control of a signal of a first scanning signal terminal. The leak-proof sub-circuit is configured to write a signal of the fifth node into a first node under control of a signal of a second scanning signal terminal.
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公开(公告)号：US20230419878A1
公开(公告)日：2023-12-28
申请号：US18466619
申请日：2023-09-13
发明人： Guangliang SHANG , Jie ZHANG , Jiangnan LU , Mei LI , Libin LIU
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G2300/0426 , G09G2300/0842 , G09G2310/0267 , G09G2330/021
摘要： A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit controls to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit controls to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal.
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公开(公告)号：US20230180551A1
公开(公告)日：2023-06-08
申请号：US17923934
申请日：2021-11-04
发明人： Jiangnan LU , Libin LIU , Guangliang SHANG , Long HAN , Yu FENG , Li WANG , Mei LI
IPC分类号： H10K59/131 , H10K59/12
CPC分类号： H10K59/131 , H10K59/1201 , H10K59/124
摘要： A display panel includes: a substrate; at least one first signal line disposed on the substrate and located in a peripheral region; at least one second signal line disposed on the substrate and located in the peripheral region; an insulating layer covering the at least one first signal line and the at least one second signal line; and a shielding signal line covering the at least one groove. The at least one second signal line and the at least one first signal line are arranged in a same layer. A surface of the insulating layer away from the substrate has at least one groove. An orthogonal projection, on the substrate, of a bottom surface of a groove is located between orthogonal projections, on the substrate, of a first signal line and a second signal line.
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公开(公告)号：US20230020923A1
公开(公告)日：2023-01-19
申请号：US17948576
申请日：2022-09-20
发明人： Yipeng CHEN , Lujiang HUANGFU , Libin LIU
IPC分类号： H01L27/32 , G09G3/3233
摘要： A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.
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公开(公告)号：US20220375392A1
公开(公告)日：2022-11-24
申请号：US17771102
申请日：2021-05-20
发明人： Yuhan QIAN , Libin LIU , Long HAN
摘要： A display panel and a display device. The display panel comprises a transition region, and further comprises: a base substrate; multiple pixel units located on the side of the base substrate and integrated in the transition region; and a first gate drive circuit located on the side of the base substrate facing the pixel units, integrated in the transition region, and comprising a first shift register unit and a first signal line group. The first signal line group comprises a first signal line segment group used for providing a drive signal for the first shift register unit. The base substrate comprises multiple integration portions which are located between orthographic projections of two adjacent pixel units in the same row on the base substrate.
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公开(公告)号：US20220367730A1
公开(公告)日：2022-11-17
申请号：US17765289
申请日：2021-04-02
发明人： Yuhan QIAN , Libin LIU
IPC分类号： H01L29/786 , G09G3/20 , H01L27/12 , H01L29/66 , G11C19/28
摘要： Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate includes a first transistor having a double gate structure, and further includes an active layer arranged on one side of the base substrate and a first conductive layer. The active layer includes a first conductor portion connected between a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and a second semiconductor portion forming a channel region of the first transistor. The first conductive layer includes a first conductive portion connected to a stable voltage source, an orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate, and the first conducting portion and the first conductor portion form two electrodes of a parallel-plate capacitor.
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公开(公告)号：US20220367596A1
公开(公告)日：2022-11-17
申请号：US17762692
申请日：2021-04-15
发明人： Yipeng CHEN , Lujiang HUANGFU , Libin LIU
IPC分类号： H01L27/32
摘要： The present disclosure provides a display panel and a method of manufacturing the same and a display device. In a sub-pixel driving circuit of the display panel, a gate electrode of a driving transistor is coupled to a second electrode of a second transistor through a fourth conductive connection portion, and a second electrode plate of a storage capacitor is coupled to a second electrode of a first transistor through a third conductive connection portion, a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to a gate line pattern in the corresponding sub-pixel area; orthographic projection of the gate line pattern on the substrate does not overlap orthographic projection of the third conductive connecting portion on the substrate, and/or does not overlap orthographic projection of the fourth conductive connection portion on the substrate.
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公开(公告)号：US20220328611A1
公开(公告)日：2022-10-13
申请号：US17435363
申请日：2021-03-15
发明人： Jiangnan LU , Libin LIU , Jie ZHANG , Mei LI , Yuhan QIAN , Shiming SHI
摘要： The display substrate includes: a substrate, an auxiliary cathode layer, a first insulating layer, an anode layer, a second insulating layer, and a cathode layer that are sequentially stacked on the substrate in a direction away from the substrate; the anode layer includes a plurality of anode patterns spaced apart from each other, and an anode spacing area is formed between adjacent anode patterns; an orthographic projection of the auxiliary cathode layer on the substrate and an orthographic projection of the cathode layer on the substrate have an auxiliary overlapping area, and the auxiliary cathode layer is electrically connected to the cathode layer through a connection via hole in the auxiliary overlapping area; an orthographic projection of the connection via hole on the substrate is located inside the orthographic projection of the anode spacing area on the substrate.
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