公开(公告)号：US20130056825A1

公开(公告)日：2013-03-07

申请号：US13225349

申请日：2011-09-02

申请人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

发明人： Chien-Chung Chen ,  Ming-Tung Lee ,  Shih-Chin Lien ,  Shyi-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L21/265 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

摘要翻译： 公开了形成半导体器件的半导体器件和方法，其中半导体器件在器件的源极和漏极区域中包括用于改善器件的Ron-sp和BVD特性的附加注入区域。 器件包括形成在器件衬底中分离第一和第二注入区域的沟道区域上的栅电极。 第一植入区域具有第一导电类型，并且第二植入区域具有第二导电类型。 源极扩散区域形成在第一注入区域中，并且漏极扩散区域形成在第二注入区域中。

公开(公告)号：US08354716B2

公开(公告)日：2013-01-15

申请号：US12830178

申请日：2010-07-02

申请人： Hsueh I Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

发明人： Hsueh I Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66681

摘要： A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.

摘要翻译： 一种在相对高电压应用中使用的半导体器件，包括衬底，用作半导体器件的高电压n阱（HVNW）的衬底中的第一n型阱区，一对第二n型阱 第一n型阱区中的第一n型阱区中的p型区，第二n型阱区之间的基板上的一对导电区域， 以及用作半导体器件的n型掩埋层（NBL）的多个n型区域，其中NBL位于第一n型区域下方并分散在衬底中。

公开(公告)号：US5849360A

公开(公告)日：1998-12-15

申请号：US670259

申请日：1996-06-20

申请人： Jow-Lay Huang ,  Ming-Tung Lee

发明人： Jow-Lay Huang ,  Ming-Tung Lee

IPC分类号： C04B35/593 ,  C04B35/628 ,  C04B41/50 ,  C04B41/87 ,  C23C16/34 ,  C23C16/44 ,  B05D3/02

CPC分类号： C04B35/62884 ,  C04B35/593 ,  C04B35/62836 ,  C04B35/62897 ,  C04B41/009 ,  C04B41/5068 ,  C04B41/87 ,  C23C16/34 ,  C23C16/4417 ,  C04B2235/3217 ,  C04B2235/3225 ,  C04B2235/3843 ,  C04B2235/3878 ,  C04B2235/3886 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/6562 ,  C04B2235/6565 ,  C04B2235/6567 ,  C04B2235/77 ,  C04B2235/96

摘要： A tube chemical vapor deposition method of preparing titanium carbide/silicon nitride (TiC/Si.sub.3 N.sub.4) composites. To prepare such composites, titanium carbide (TiC) is first coated with a homogeneous layer of titanium nitride (Ti.sub.3 N.sub.4). A gas mixture of titanium chloride (TiCl.sub.4), nitrogen (N.sub.2), hydrogen (H.sub.2) with an appropriate ratio is introduced into a reaction chamber where the tube chemical vapor deposition takes place. The temperature of the reaction for the sintering process is between 900.degree. C. to 1200.degree. C., under a total pressure of 1 atm. While maintaining a constant temperature for 1 to 2 hours, deposition of titanium nitride (Ti.sub.3 N.sub.4) onto titanium carbide (TiC) powder takes place. The adoption of the simple tube chemical vapor deposition technique for the present invention not only enables a mass production of homogeneously coated titanium carbide (TiC) particulates, but also further enhances the hardness and toughness as well as other mechanical properties of silicon based composites, such as a titanium carbide/silicon nitride (TiC/Si.sub.3 N.sub.4) composite.

摘要翻译： 一种制备碳化钛/氮化硅（TiC / Si3N4）复合材料的管化学气相沉积方法。 为了制备这种复合材料，首先用均匀的氮化钛（Ti 3 N 4）层涂覆碳化钛（TiC）。 将具有适当比例的氯化钛（TiCl 4），氮（N 2），氢（H 2）的气体混合物引入到发生管化学气相沉积的反应室中。 烧结过程的反应温度为900〜1200℃，总压力为1个大气压。 在保持恒温1〜2小时的同时，将氮化钛（Ti 3 N 4）沉积到碳化钛（TiC）粉末上。 采用本发明的简单管化学气相沉积技术不仅可以大量生产均匀涂覆的碳化钛（TiC）颗粒，而且可以进一步提高硅基复合材料的硬度和韧性以及其它机械性能，例如 作为碳化钛/氮化硅（TiC / Si 3 N 4）复合体。

公开(公告)号：US5777536A

公开(公告)日：1998-07-07

申请号：US857867

申请日：1997-05-16

申请人： Wen-Fong Lee ,  Ming-Hung Lee ,  Ming-Tung Lee ,  Ming-Yu Lee

发明人： Wen-Fong Lee ,  Ming-Hung Lee ,  Ming-Tung Lee ,  Ming-Yu Lee

IPC分类号： H01H9/04 ,  H01H36/00 ,  H01H71/52 ,  H01H9/00

CPC分类号： H01H71/521 ,  H01H36/0073 ,  H01H9/04

摘要： A sealed electric switch assembly comprises a magnetic control assembly having first and second magnetic members which is mounted to a top wall of a sealed casing, and an elongated plate having third and fourth magnetic members which is mounted oppositely to the first and second magnetic members so that the elongated plate member can be attracted and repulsed magnetically by the magnetic control assembly. A linkage mechanism is mounted adjacent to the elongated plate member for moving a movable contact of a movable arm to connect and disconnect with a stationary contact. A rotary assembly and a tripping assembly are mounted above the linkage mechanism and over an electromagnet.

摘要翻译： 密封电开关组件包括具有安装到密封壳体的顶壁的第一和第二磁性构件的磁控制组件和具有与第一和第二磁性构件相对地安装的第三和第四磁性构件的细长板， 细长板构件可以被磁控制组件磁吸引并排斥。 连接机构安装在细长板构件附近，用于移动可动臂的可动触点以与固定触点连接和断开。 旋转组件和跳闸组件安装在连杆机构上方和电磁体上方。

公开(公告)号：US20120001260A1

公开(公告)日：2012-01-05

申请号：US12830178

申请日：2010-07-02

申请人： Hsueh I. Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

发明人： Hsueh I. Huang ,  Ming-Tung Lee ,  Shyi-Yuan Wu

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66681

摘要： A semiconductor device for use in a relatively high voltage application that comprises a substrate, a first n-type well region in the substrate to serve as a high voltage n-well (HVNW) for the semiconductor device, a pair of second n-type well regions in the first n-type well region, a p-type region in the first n-type well region between the second n-type well regions, a pair of conductive regions on the substrate between the second n-type well regions, and a number of n-type regions to serve as n-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are located below the first n-type region and dispersed in the substrate.

摘要翻译： 一种在相对高电压应用中使用的半导体器件，包括衬底，用作半导体器件的高电压n阱（HVNW）的衬底中的第一n型阱区，一对第二n型阱 第一n型阱区中的第一n型阱区中的p型区，第二n型阱区之间的基板上的一对导电区域， 以及用作半导体器件的n型掩埋层（NBL）的多个n型区域，其中NBL位于第一n型区域下方并分散在衬底中。

公开(公告)号：US06881619B1

公开(公告)日：2005-04-19

申请号：US10707707

申请日：2004-01-06

申请人： Ming-Tung Lee ,  Chao-Ching Lin

发明人： Ming-Tung Lee ,  Chao-Ching Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8247

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  Y10S438/954

摘要： A method for fabricating a non-volatile memory is provided. A stacked structure including a tunneling layer, a trapping layer, a barrier layer, and a control gate is formed on a substrate. A source region and a drain region are formed beside the stacked structure in the substrate. A silicon oxide spacer is formed on the sidewalls of the stacked structure. An ultraviolet-resistant lining layer is formed on the surfaces of the substrate and the stacked structure to prevent the ultraviolet light from penetrating into the trapping layer. A dielectric layer is formed on the ultraviolet-resistant lining layer. A contact being electrically connected to the control gate is formed in the dielectric layer. A conducting line electrically connected to the contact is formed on the dielectric layer. A lost-surface-charge lining layer is formed on the surfaces of the dielectric layer and the conducting line to reduce the antenna effect.

摘要翻译： 提供了一种用于制造非易失性存储器的方法。 在衬底上形成包括隧道层，俘获层，阻挡层和控制栅极的堆叠结构。 源极区域和漏极区域形成在基板的层叠结构的旁边。 在堆叠结构的侧壁上形成氧化硅隔离物。 在基板和堆叠结构的表面上形成防紫外线衬层，以防止紫外线侵入捕获层。 在耐紫外线衬层上形成介电层。 在电介质层中形成电连接到控制栅极的触点。 在电介质层上形成与触点电连接的导线。 在介电层和导电线的表面上形成失去表面的电荷衬里层，以减少天线效应。