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11.发明申请Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor 失效用于为无序微处理器恢复寄存器映射器状态的方法和系统公开(公告)号：US20080195850A1
公开(公告)日：2008-08-14
申请号：US11674754
申请日：2007-02-14
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译： 一种恢复无序微处理器的寄存器映射器状态的方法。 处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。 指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态 位图中的数据结构。
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12.发明申请Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies 有权在使用虚假依赖关系的乱序处理器中发布使用说明书公开(公告)号：US20100251016A1
公开(公告)日：2010-09-30
申请号：US12409981
申请日：2009-03-24
CPC分类号： G06F11/0793 , G06F9/3838 , G06F9/3851 , G06F9/3863 , G06F9/3885 , G06F11/0721
摘要： A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.
摘要翻译： 提供了发出指令的机制。 指令调度单元接收用于发送到多个执行单元之一的指令。 指令调度单元分析标签寄存器以确定与先前指令相关联的先前标签是否已经存储在标签寄存器中。 指令调度单元响应于与先前指令相关联的先前的标签不能存储在标签寄存器中，存储与标签寄存器中的指令相对应的标签。 指令调度单元将指令发送到多个执行单元中的一个执行单元。
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13.发明授权Method and system for restoring register mapper states for an out-of-order microprocessor 失效用于恢复无序微处理器的寄存器映射器状态的方法和系统公开(公告)号：US07689812B2
公开(公告)日：2010-03-30
申请号：US11674754
申请日：2007-02-14
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译： 一种恢复无序微处理器的寄存器映射器状态的方法。 处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。 指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态 位图中的数据结构。
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14.发明授权公开(公告)号：US08386753B2
公开(公告)日：2013-02-26
申请号：US12423561
申请日：2009-04-14
IPC分类号： G06F9/38
CPC分类号： G06F9/485
摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.
摘要翻译： 提供线程完成仲裁的机制。 该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程 的线程，在两个以上的线程中，用于完成处理器内的执行。 该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。 线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。 线程的第一个子集和线程的第二个子集具有彼此不同的线程。
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15.发明授权Enhanced single threaded execution in a simultaneous multithreaded microprocessor 有权在同时多线程微处理器中增强单线程执行公开(公告)号：US07827389B2
公开(公告)日：2010-11-02
申请号：US11763736
申请日：2007-06-15
申请人： Hung Q. Le , Dung Q. Nguyen
发明人： Hung Q. Le , Dung Q. Nguyen
CPC分类号： G06F9/3885 , G06F9/30105 , G06F9/30116 , G06F9/3012 , G06F9/30141 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. The processing unit dispatches a first set of instructions in order from a first buffer for execution. The processing unit receives updated results from the execution of the first set of instructions. The processing unit updates, in a first register, at least one register entry associated with each instruction in the first set of instructions, with the updated results. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to the completed execution of the first set of instructions from the first buffer, the processing unit copies the set of entries from the first register to a second register.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于增强处理单元中独立负载的执行。 处理单元从第一缓冲器依次调度第一组指令以执行。 处理单元从执行第一组指令接收更新的结果。 处理单元在第一寄存器中更新与第一组指令中的每个指令相关联的至少一个寄存器条目以及更新的结果。 处理单元确定来自第一缓冲器的第一组指令是否已经完成执行。 响应于来自第一缓冲器的第一组指令的完成执行，处理单元将该组条目从第一寄存器复制到第二寄存器。
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16.发明申请System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor 有权用于在微处理器的负载前端机制下实现硬件支持的线程辅助的系统和方法公开(公告)号：US20090106538A1
公开(公告)日：2009-04-23
申请号：US11877391
申请日：2007-10-23
申请人： James W. Bishop , Hung Q. Le , Dung Q. Nguyen , Wolfram Sauer , Benjamin W. Stolt , Michael T. Vaden
发明人： James W. Bishop , Hung Q. Le , Dung Q. Nguyen , Wolfram Sauer , Benjamin W. Stolt , Michael T. Vaden
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/383
摘要： The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.
摘要翻译： 本发明包括一种用于在微处理器的负载初始化机制下实现硬件支持的线程辅助的系统和方法。 根据本发明的实施例，当微处理器的一个线程处于睡眠模式时，可以激活硬件线程辅助模式。 当加载前瞻模式被激活时，固定点单元将一个或多个架构设施的内容从活动线程复制到第一个非活动线程中的相应的架构设施。 加载存储单元在负载前瞻模式中执行至少一个推测负载，并将至少一个推测负载的结果写入第一非活动线程中的复制架构设施。
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17.发明申请Enhanced Single Threaded Execution in a Simultaneous Multithreaded Microprocessor 有权在同时多线程微处理器中增强单线程执行公开(公告)号：US20080313422A1
公开(公告)日：2008-12-18
申请号：US11763736
申请日：2007-06-15
申请人： Hung Q. Le , Dung Q. Nguyen
发明人： Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/30105 , G06F9/30116 , G06F9/3012 , G06F9/30141 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. The processing unit dispatches a first set of instructions in order from a first buffer for execution. The processing unit receives updated results from the execution of the first set of instructions. The processing unit updates, in a first register, at least one register entry associated with each instruction in the first set of instructions, with the updated results. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to the completed execution of the first set of instructions from the first buffer, the processing unit copies the set of entries from the first register to a second register.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于增强处理单元中独立负载的执行。 处理单元从第一缓冲器依次调度第一组指令以执行。 处理单元从执行第一组指令接收更新的结果。 处理单元在第一寄存器中更新与第一组指令中的每个指令相关联的至少一个寄存器条目以及更新的结果。 处理单元确定来自第一缓冲器的第一组指令是否已经完成执行。 响应于来自第一缓冲器的第一组指令的完成执行，处理单元将该组条目从第一寄存器复制到第二寄存器。
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18.发明申请DYNAMIC RECALCULATION OF RESOURCE VECTOR AT ISSUE QUEUE FOR STEERING OF DEPENDENT INSTRUCTIONS 有权发布问题动态资源向量的动态调整，用于指导相关指示公开(公告)号：US20080133890A1
公开(公告)日：2008-06-05
申请号：US12013572
申请日：2008-01-14
申请人： Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto , Raymond C. Yeung
发明人： Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto , Raymond C. Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译： 一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。 在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。 分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。
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公开(公告)号：US07194603B2
公开(公告)日：2007-03-20
申请号：US10422026
申请日：2003-04-23
CPC分类号： G06F9/3867 , G06F9/3851 , G06F9/3855 , G06F9/3861
摘要： A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of incoming flush sources by thread. This uses the forward link array by flush source to determine the next instruction group following the group indicated by the flush source (for example, for mispredicts and load/store flush-next type flushes). Presentation of flush completion table entry numbers or instruction group identifiers (Gtags) to the flush table for computation of oldest flushed group tag corresponding to each thread. The flush selection cycle wherein the flush table outputs are compared against saved versions of all the flush Gtags presented to determine which flush source matches the oldest group output from the flush table. The flush source information is used with the selected oldest Gtag to determine the appropriate additional flushing action to take during the flush cycle.
摘要翻译： 使用动态共享组完成表（GCT）和冲洗表处理SMT处理器中的刷新的方法包括通过线程识别输入的刷新源。 这通过flush源使用前向链接数组来确定闪存源指示的组之后的下一个指令组（例如，用于错误预测和加载/存储flush-next类型刷新）。 将刷新完成表条目号或指令组标识符（Gtags）呈现给刷新表，以计算与每个线程相对应的最旧刷新组标签。 将刷新表输出的刷新选择循环与所提供的所有刷新Gtags的保存版本进行比较，以确定哪个flush源与flush表中最早的组输出相匹配。 冲洗源信息与所选最旧的Gtag一起使用，以确定在冲洗循环期间采取的适当的额外冲洗动作。
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20.发明授权Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system 失效获取和存储缓冲区，使数据处理系统中的存储器指令无序执行
公开(公告)号：US5465336A
公开(公告)日：1995-11-07
申请号：US269868
申请日：1994-06-30
申请人： Benjamin T. Imai , Hung Q. Le , Dung Q. Nguyen
发明人： Benjamin T. Imai , Hung Q. Le , Dung Q. Nguyen
CPC分类号： G06F9/3834
摘要： A method and device for handling fetch and store requests in a data processing system is provided. A fetch and store buffer comprises a store queue, a fetch queue, a register, a comparator, and a controller. The store queue and the fetch queue receive requests from one or more execution units. When the fetch queue receives a fetch request from an execution unit, it sets a mark in a field associated with the request indicating the store queue entries present at the time the fetch request is entered, and further, removing a mark from the field when the associated store queue entry is drained. The controller gates a copy of the fetch request in the fetch queue into the memory unit address register and to the memory unit, when the memory unit is ready to accept a request. The comparator determines if there is a dependency between the gated request in the memory unit address register and any store queue entries marked in the gated request's field. When a dependency is determined by the comparator, the controller drains the store queue entries marked in the pending fetch request's field from the store queue prior to draining the fetch queue entries.
摘要翻译： 提供了一种在数据处理系统中处理提取和存储请求的方法和装置。 获取和存储缓冲器包括存储队列，获取队列，寄存器，比较器和控制器。 存储队列和获取队列从一个或多个执行单元接收请求。 当抓取队列从执行单元接收到提取请求时，它在与请求相关联的字段中设置一个标记，指示在输入提取请求时存在的存储队列条目，并且进一步，当字段 关联的存储队列条目被排除。 当存储器单元准备好接受请求时，控制器将获取队列中的提取请求的副本写入存储器单元地址寄存器和存储器单元。 比较器确定存储器单元地址寄存器中的门控请求与门控请求字段中标记的任何存储队列条目之间是否存在依赖关系。 当依赖关系由比较器确定时，控制器在排出提取队列条目之前从存储队列中排出在待处理的提取请求的字段中标记的存储队列条目。
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