公开(公告)号：US08386753B2

公开(公告)日：2013-02-26

申请号：US12423561

申请日：2009-04-14

申请人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/38

CPC分类号： G06F9/485

摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.

摘要翻译： 提供线程完成仲裁的机制。 该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程 的线程，在两个以上的线程中，用于完成处理器内的执行。 该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。 线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。 线程的第一个子集和线程的第二个子集具有彼此不同的线程。

公开(公告)号：US20100262967A1

公开(公告)日：2010-10-14

申请号：US12423561

申请日：2009-04-14

申请人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： Susan E. Eisen ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/46

CPC分类号： G06F9/485

摘要： A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.

摘要翻译： 提供线程完成仲裁的机制。 该机制包括在处理器中同时执行多于两个指令的线程，在多于两个线程中从线程的第一子集中选择第一线程，以完成处理器内的执行，以及从第二子集中选择第二线程 的线程，在两个以上的线程中，用于完成处理器内的执行。 该机制还包括通过将执行第一和第二线程的结果提交到与处理器相关联的存储设备来完成第一和第二线程的执行。 线程的第一子集或线程的第二子集中的至少一个包括来自多于两个线程的两个或多个线程。 线程的第一个子集和线程的第二个子集具有彼此不同的线程。

公开(公告)号：US09489207B2

公开(公告)日：2016-11-08

申请号：US12423495

申请日：2009-04-14

申请人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.

摘要翻译： 提供了用于部分刷新处理的机制，每个指令组具有多个分支。 指令提取单元将指令分组分组。 组可以包括浮动分支指令和边界分支指令。 对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。 指令排序单元使用GCT来管理每个优秀组内的指令完成。 因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。 因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

公开(公告)号：US20100262807A1

公开(公告)日：2010-10-14

申请号：US12423495

申请日：2009-04-14

申请人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

发明人： William E. Burky ,  Brian R. Mestan ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Benjamin W. Stolt

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857

摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.

摘要翻译： 提供了用于部分刷新处理的机制，每个指令组具有多个分支。 指令提取单元将指令分组分组。 组可以包括浮动分支指令和边界分支指令。 对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。 指令排序单元使用GCT来管理每个优秀组内的指令完成。 因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。 因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

公开(公告)号：US10067765B2

公开(公告)日：2018-09-04

申请号：US13470386

申请日：2012-05-14

申请人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/38 ,  G06F9/30

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

公开(公告)号：US20130305022A1

公开(公告)日：2013-11-14

申请号：US13470386

申请日：2012-05-14

申请人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

发明人： Susan E. Eisen ,  Hung Q. Le ,  Bryan J. Lloyd ,  Dung Q. Nguyen ,  David S. Ray ,  Benjamin W. Stolt ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/312

CPC分类号： G06F9/30087 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861

摘要： Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.

摘要翻译： 在处理器中提供用于执行比先前调度的同步（sync）指令更年轻的指令的机制。 处理器的指令定序器单元调度同步指令。 同步指令被发送到处理器外部的一个或多个设备的嵌套。 指令定序器单元在调度同步指令之后调度后续指令。 调度同步指令后的后续指令的调度是在收到来自嵌套的同步确认响应之前执行的。 指令定序器单元基于后续指令的完成是否依赖于从嵌套接收到同步确认和完成同步指令而执行后续指令的完成。

公开(公告)号：US08131976B2

公开(公告)日：2012-03-06

申请号：US12422595

申请日：2009-04-13

申请人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, Jr.

发明人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, Jr.

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F9/3802 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3861

摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

摘要翻译： 在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。 这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。 所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。 此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

公开(公告)号：US20100262806A1

公开(公告)日：2010-10-14

申请号：US12422595

申请日：2009-04-13

申请人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, JR.

发明人： Richard W. Doing ,  Susan E. Eisen ,  David S. Levitan ,  Kevin N. Magill ,  Brian R. Mestan ,  Balaram Sinharoy ,  Benjamin W. Stolt ,  Jeffrey R. Summers ,  Albert J. Van Norstrand, JR.

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3861

摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

摘要翻译： 在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。 这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。 所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。 此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

公开(公告)号：US07779234B2

公开(公告)日：2010-08-17

申请号：US11877391

申请日：2007-10-23

申请人： James W. Bishop ,  Hung Q. Le ,  Dung Q. Nguyen ,  Wolfram Sauer ,  Benjamin W. Stolt ,  Michael T. Vaden

发明人： James W. Bishop ,  Hung Q. Le ,  Dung Q. Nguyen ,  Wolfram Sauer ,  Benjamin W. Stolt ,  Michael T. Vaden

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/383

摘要： The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.

摘要翻译： 本发明包括一种用于在微处理器的负载初始化机制下实现硬件支持的线程辅助的系统和方法。 根据本发明的实施例，当微处理器的一个线程处于睡眠模式时，可以激活硬件线程辅助模式。 当加载前瞻模式被激活时，固定点单元将一个或多个架构设施的内容从活动线程复制到第一个非活动线程中的相应的架构设施。 加载存储单元在负载前瞻模式中执行至少一个推测负载，并将至少一个推测负载的结果写入第一非活动线程中的复制架构设施。

公开(公告)号：US20110302392A1

公开(公告)日：2011-12-08

申请号：US12793718

申请日：2010-06-04

申请人： Christopher M. Abernathy ,  Hung Q. Le ,  Dung Q. Nguyen ,  Benjamin W. Stolt

发明人： Christopher M. Abernathy ,  Hung Q. Le ,  Dung Q. Nguyen ,  Benjamin W. Stolt

IPC分类号： G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30 ,  G06F9/3851 ,  G06F9/3857

摘要： A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.

摘要翻译： 一种用于跟踪处理器中的指令的方法和装置。 处理器中的完成单元接收到添加到表中以形成接收到的指令组的指令组。 响应于接收到接收到的指令组，完成单元确定是否存在包含在第一位置中的先前存储的指令组的条目，并且具有用于存储接收到的指令组的空间。 响应于存在的条目，完成单元将接收到的指令组存储在条目中的第二位置，以形成存储的指令组。