公开(公告)号：US06461897B2

公开(公告)日：2002-10-08

申请号：US09854486

申请日：2001-05-15

Applicant: Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao

Inventor： Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao

IPC: H01L2144

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/01087 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract translation: 多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。 半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线 芯片以允许其引线接合。 因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。 这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

公开(公告)号：US06455353B2

公开(公告)日：2002-09-24

申请号：US09925688

申请日：2001-08-10

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2144

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L2224/274 ,  H01L2924/01079

Abstract: A method of manufacturing chip scale packages at wafer level, comprising the steps of: a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes; b) forming a dam enclosing the perimeter of the wafer; c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and e) dicing the wafer according to the exposed scribe lines as positioning reference marks.

Abstract translation: 一种在晶片级制造芯片尺寸封装的方法，包括以下步骤：a）提供具有有源背面和背面的晶片，晶片的有源表面具有限定单个芯片的多个划线，并且每个芯片具有 多个电极; b）形成围绕晶片周边的坝; c）用模塑料填充由坝封闭的区域以封装晶片的活性表面; d）去除坝体以暴露在晶片的有效表面上的坝所覆盖的划痕线; 和e）根据暴露的划痕线将晶片切割为定位参考标记。

公开(公告)号：US06359340B1

公开(公告)日：2002-03-19

申请号：US09628676

申请日：2000-07-28

Applicant: Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao ,  Jian Wen Chen

Inventor： Chun Hung Lin ,  Kuang-Hui Chen ,  Shyh-Wei Wang ,  Su Tao ,  Jian Wen Chen

IPC: H05K706

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract translation: 多芯片模块具有至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。 在一些实施例中，半导体芯片可以具有仅沿着其两个相互垂直的侧边缘的多个接合焊盘。 半导体芯片以堆叠方式安装到基板上，其中上部芯片以下述方式附接到下部芯片的有源表面，即，上部芯片的任何部分不影响下部芯片的每个焊盘的垂直视线 芯片以允许其引线接合。 因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。 这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

公开(公告)号：US06348729B1

公开(公告)日：2002-02-19

申请号：US09390695

申请日：1999-09-07

Applicant: Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

Inventor： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

IPC: H01L2352

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Abstract translation: 半导体芯片封装通常包括引线框架，半导体管芯和塑料封装体。 引线框架包括多个引线和窗垫。 窗垫通过连接杆连接到引线框架。 多个引线的内端限定中心区域。 窗垫设置在中心区域中并且具有限定在其中的开口。 半导体管芯设置在窗垫的开口中，并且在其活性表面上形成有多个接合焊盘。 引线的内端通过多根接合线与半导体管芯上的焊盘相互连接。 引线框架，半导体管芯和接合线被封装在塑料封装主体中，其中引线框架的下表面和半导体管芯的后表面通过塑料封装主体露出。

公开(公告)号：US06238952B1

公开(公告)日：2001-05-29

申请号：US09516024

申请日：2000-02-29

Applicant: Chun Hung Lin

Inventor： Chun Hung Lin

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/4821 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K3/06 ,  H05K3/202 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.