公开(公告)号：US20070267758A1

公开(公告)日：2007-11-22

申请号：US11539130

申请日：2006-10-05

申请人： Su TAO ,  Chi CHIU ,  Sung WU

发明人： Su TAO ,  Chi CHIU ,  Sung WU

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/315 ,  H01L23/66 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprises a first chip, a substrate, a middle layer, a second chip, and an encapsulant. The first chip has an active surface and a high-frequency element defining a high-frequency area on the active surface. The substrate supports the first chip and is electrically connected to the first chip. The middle layer is disposed on the first chip and has a recess corresponding to the high-frequency area. The second chip is disposed on the middle layer and electrically connected to either the first chip or the substrate. The encapsulant encapsulates the first chip, the middle layer, the second chip, and a part of the substrate.

摘要翻译： 半导体封装包括第一芯片，基板，中间层，第二芯片和密封剂。 第一芯片具有有源表面和限定有源表面上的高频区域的高频元件。 基板支撑第一芯片并电连接到第一芯片。 中间层设置在第一芯片上并且具有对应于高频区域的凹部。 第二芯片设置在中间层上并与第一芯片或基板电连接。 密封剂封装第一芯片，中间层，第二芯片和基板的一部分。

公开(公告)号：US07253529B2

公开(公告)日：2007-08-07

申请号：US11026797

申请日：2004-12-31

申请人： Su Tao ,  Yu-Fang Tsai

发明人： Su Tao ,  Yu-Fang Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

摘要翻译： 本发明涉及一种多芯片封装结构，包括第一基板，第一芯片，子封装和第一模塑料。 第一芯片附接到第一基板。 第一模塑料封装第一芯片，子封装和第一衬底的顶表面。 子封装的底表面附接到第一芯片。 该子组件包括第二衬底，第二芯片和第二模塑料。 第二基板具有顶表面和底表面，并且电连接到第一芯片。 第二芯片附接到第二芯片电连接到的第二基板的顶表面。 第二模塑料包封第二芯片和第二基板顶表面的一部分。 由此，可以减少由多个常规封装结构的平行布置引起的相对大的面积，并且不需要重新设计信号传输路径。

公开(公告)号：US07151308B2

公开(公告)日：2006-12-19

申请号：US10791896

申请日：2004-03-04

申请人： Su Tao ,  Shih Chang Lee

发明人： Su Tao ,  Shih Chang Lee

IPC分类号： H01L23/58

CPC分类号： H01L23/36 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor chip package includes an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate.

摘要翻译： 半导体芯片封装包括互连衬底，中心衬底，外围衬底和夹在互连衬底和中心衬底之间的半导体芯片。 互连基板具有用于接收半导体芯片的凹腔。 外围基板与中心基板分离，从而减小由半导体芯片封装的CTE失配引起的应力。 此外，中心基板和周边基板都与机械地和电连接到互连基板，使得半导体芯片通过中心基板和互连基板电连接到外围基板。

公开(公告)号：US07002805B2

公开(公告)日：2006-02-21

申请号：US10747037

申请日：2003-12-30

申请人： Shih-Chang Lee ,  Su Tao ,  Chian-Chi Lin

发明人： Shih-Chang Lee ,  Su Tao ,  Chian-Chi Lin

IPC分类号： H05K7/20

CPC分类号： H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： A thermal enhance multi-chips module (MCM) package mainly comprises a first package, a first carrier, a second package, a second carrier, an intermediate substrate and a cap-like heat spreader. The intermediate substrate has an opening. The first carrier and the second carrier are electrically connected to the first package and the second package respectively. The second package is accommodated in the opening and electrically connected to the first package via the first carrier, the second carrier and the intermediate carrier. The cap-like heat spreader has a supporting portion and an alignment portion wherein the supporting portion is connected to the alignment portion to define a cavity. The cavity not only accommodates the first package, the first carrier, the second package, the second carrier and the intermediate substrate but also provides alignment mechanism by the supporting portion and the alignment portion to prevent the dislocation after all the components of the thermal enhance MCM package are connected with each other. Furthermore, the first carrier has a first side and the second carrier has a second side. The first side and the second side both have grounding portions, for example recessed portions and metal layers, for providing a ground shielding of the first package and the second package against the outside. In addition, the grounding portions also provide thermal paths to increase the ability of the heat dissipation. Besides, a method for manufacturing the thermal enhance MCM package is provided.

摘要翻译： 热增强多芯片模块（MCM）封装主要包括第一封装，第一载体，第二封装，第二载体，中间基板和帽状散热器。 中间基板具有开口。 第一载体和第二载体分别电连接到第一封装和第二封装。 第二包装被容纳在开口中并且经由第一载体，第二载体和中间载体电连接到第一封装。 帽状散热器具有支撑部分和对准部分，其中支撑部分连接到对准部分以限定空腔。 空腔不仅容纳第一封装，第一载体，第二封装，第二载体和中间基板，而且还通过支撑部分和对准部分提供对准机构，以防止在热增强MCM的所有部件的所有部件之后的位错 包装相互连接。 此外，第一载体具有第一侧，第二载体具有第二侧。 第一侧和第二侧都具有接地部分，例如凹部和金属层，用于提供第一包装和第二包装的接地屏蔽抵抗外部。 此外，接地部分还提供热路径以增加散热能力。 此外，还提供了一种用于制造热增强MCM封装的方法。

公开(公告)号：US20060001136A1

公开(公告)日：2006-01-05

申请号：US11170309

申请日：2005-06-29

申请人： Su Tao ,  Chi-Wen Chang

发明人： Su Tao ,  Chi-Wen Chang

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.

公开(公告)号：US06967153B2

公开(公告)日：2005-11-22

申请号：US10248688

申请日：2003-02-10

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： H01L21/60 ,  H05K3/34 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3484 ,  H05K2201/09863 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0594

摘要： A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump. Solder material is deposited into the openings and then a reflow process is conducted fusing the solder material and the pre-formed bump together to form a spherical bump. The pre-formed bump and the solder material may be fabricated using different constituents.

摘要翻译： 提供了一种用于在其上具有多个接合焊盘的晶片上形成凸块的凸块制造工艺。 具有暴露各个接合焊盘的多个开口的图案化焊接掩模层形成在晶片上。 通过底部的横截面积中的开口面积以及通过开口的顶部的开口面积比通过中间部分的横截面积的开口面积小， 部分开幕。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料熔合在一起，以在开口内形成球形凸块。 最后，去除焊接掩模层。 此外，在晶片上形成图案化的焊料掩模层之前，至少具有暴露预形成的凸块的开口之前，可以在晶片的焊盘上形成预形成的凸块。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料和预形成的凸块熔合在一起形成球形凸块。 可以使用不同的成分制造预形成的凸块和焊料材料。

公开(公告)号：US20050233571A1

公开(公告)日：2005-10-20

申请号：US10921967

申请日：2004-08-20

申请人： Su Tao ,  Min-Lung Huang ,  Ho-Ming Tong

发明人： Su Tao ,  Min-Lung Huang ,  Ho-Ming Tong

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498

CPC分类号： H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/14051 ,  H01L2224/73203 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/30107

摘要： A semiconductor chip with bumps formed therein comprises an active surface, a plurality of bonding pads, a passivation layer, a plurality of first UBMs (under bump metallurgy), a second UBM, a plurality of first bumps, and a plurality of second bumps. The bonding pads are disposed on the active surface of the semiconductor chip. The passivation layer covers the active surface of the semiconductor chip with the pads exposed out of the passivation layer. The first UMBs are individually disposed on the bonding pads. The second UMB is disposed on at least two of the bonding pads. The first bumps are disposed on the first UMBs. The second bumps are disposed on the second UBM.

摘要翻译： 其中形成有凸起的半导体芯片包括有源表面，多个接合焊盘，钝化层，多个第一UBM（凸块下冶金），第二UBM，多个第一凸块和多个第二凸块。 接合焊盘设置在半导体芯片的有源表面上。 钝化层覆盖半导体芯片的有源表面，其中焊盘暴露在钝化层之外。 第一UMB分别设置在接合焊盘上。 第二UMB设置在至少两个接合焊盘上。 第一个颠簸位于第一个UMB上。 第二凸块设置在第二UBM上。

公开(公告)号：US20050161812A1

公开(公告)日：2005-07-28

申请号：US10907744

申请日：2005-04-14

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shou Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shou Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： H01L23/31 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/48237 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer-level package structure, applicable to a flip-chip type arrangement on a carrier having a plurality of contact points is described. This wafer-level package structure comprises a chip having a protective layer and a plurality of bonding pads and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The wafer-level package structure can further include a heat sink to enhance the heat dissipation ability of the package structure.

摘要翻译： 描述了可应用于具有多个接触点的载体上的倒装芯片型布置的晶片级封装结构。 该晶片级封装结构包括具有保护层和多个焊盘和导电层的芯片。 导电层设置在芯片的焊盘上作为接触点。 晶片级封装结构还可以包括散热器，以增强封装结构的散热能力。

公开(公告)号：US20050140022A1

公开(公告)日：2005-06-30

申请号：US11026797

申请日：2004-12-31

申请人： Su Tao ,  Yu-Fang Tsai

发明人： Su Tao ,  Yu-Fang Tsai

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/433 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

公开(公告)号：US06838762B2

公开(公告)日：2005-01-04

申请号：US10412291

申请日：2003-04-14

申请人： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

发明人： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

IPC分类号： B81B7/00 ,  H01L23/10 ,  H01L23/28 ,  H01L23/48 ,  H01L25/065 ,  H01L31/075

CPC分类号： B81B7/0041 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L23/10 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/16235 ,  H01L2924/00

摘要： A wafer-level package includes a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.

摘要翻译： 晶片级封装包括第一芯片，第二芯片和凸块环。 第一芯片具有半导体微器件，围绕半导体微器件的焊盘环，以及设置在焊盘环外部并电连接到半导体微器件用于电连接到外部电路的多个焊盘。 第二芯片具有与第一芯片的焊盘环相对应的焊盘环。 凸块环设置在第一芯片的焊盘环和第二芯片的焊盘环之间，用于接合第一芯片和第二芯片以形成密封腔。