HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS
    11.
    发明申请
    HIGH-VOLTAGE-TOLERANT ESD CLAMP CIRCUIT WITH LOW LEAKAGE CURRENT FABRICATED BY LOW-VOLTAGE CMOS PROCESS 有权
    低电压CMOS工艺制造的低漏电流高耐压ESD钳位电路

    公开(公告)号:US20110149449A1

    公开(公告)日:2011-06-23

    申请号:US12641037

    申请日:2009-12-17

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0262

    摘要: An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.

    摘要翻译: 提供了一种静电放电(ESD)钳位电路,其包括多个相同的模块电路。 第一模块电路的阳极耦合到ESD钳位电路的阴极。 每个其他模块电路的阳极耦合到先前模块电路的阴极。 最后一个模块电路的阴极耦合到ESD钳位电路的接地端。 每个模块电路包括导通路径和检测电路。 检测电路耦合到阳极,阴极和模块电路的传导路径。 当模块电路的阳极电压的上升速度超过阈值时,检测电路使导通路径导通。

    SILICON CONTROLLED RECTIFIER
    12.
    发明申请
    SILICON CONTROLLED RECTIFIER 有权
    硅控整流器

    公开(公告)号:US20090179222A1

    公开(公告)日:2009-07-16

    申请号:US12013637

    申请日:2008-01-14

    IPC分类号: H01L29/747

    摘要: A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well.

    摘要翻译: 提供了多边形布局的可控硅整流器结构。 多边形第一导电型掺杂区域位于多边形第二导电类型阱的中间。 良好成形为多边形环的第一导电类型围绕第二导电类型阱并且第二导电类型掺杂区域位于第一导电类型阱内并且形状为与第一导电类型阱同心的多边形环。

    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    13.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 有权
    静电放电保护电路

    公开(公告)号:US20110198678A1

    公开(公告)日:2011-08-18

    申请号:US12705339

    申请日:2010-02-12

    IPC分类号: H01L27/06 H01L23/60

    CPC分类号: H02H9/046 H01L27/0285

    摘要: An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

    摘要翻译: 提供一种适用于包括第一N沟道金属氧化物半导体(NMOS)晶体管的输入级电路的静电放电(ESD)保护电路。 ESD保护电路包括P沟道金属氧化物半导体(PMOS)晶体管和阻抗器件,其中PMOS晶体管具有耦合到第一NMOS晶体管的栅极的源极和耦合到第一NMOS晶体管的源极的漏极 并且阻抗器件耦合在PMOS晶体管的栅极和第一电源轨之间以执行初始ESD保护电路。 由PMOS晶体管和电阻器形成的ESD保护电路能够增加ESD保护电路的接通速度并防止输入级电路从CDM ESD事件发生。

    High-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process
    14.
    发明授权
    High-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process 有权
    采用低电压CMOS工艺制造的低漏电流高耐压ESD钳位电路

    公开(公告)号:US08422180B2

    公开(公告)日:2013-04-16

    申请号:US12641037

    申请日:2009-12-17

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0262

    摘要: An electrostatic discharge (ESD) clamp circuit is provided, which includes a plurality of identical module circuits. The anode of the first module circuit is coupled to the cathode of the ESD clamp circuit. The anode of each of the other module circuits is coupled to the cathode of the previous module circuit. The cathode of the last module circuit is coupled to the ground terminal of the ESD clamp circuit. Each module circuit includes a conduction path and a detection circuit. The detection circuit is coupled to the anode, the cathode and the conduction path of the module circuit. When the rising speed of the voltage at the anode of the module circuit surpasses a threshold value, the detection circuit makes the conduction path conducting.

    摘要翻译: 提供了一种静电放电(ESD)钳位电路,其包括多个相同的模块电路。 第一模块电路的阳极耦合到ESD钳位电路的阴极。 每个其他模块电路的阳极耦合到先前模块电路的阴极。 最后一个模块电路的阴极耦合到ESD钳位电路的接地端。 每个模块电路包括导通路径和检测电路。 检测电路耦合到阳极,阴极和模块电路的传导路径。 当模块电路的阳极电压的上升速度超过阈值时,检测电路使导通路径导通。

    ESD protection circuitry with multi-finger SCRS
    15.
    发明授权
    ESD protection circuitry with multi-finger SCRS 有权
    具有多指SCRS的ESD保护电路

    公开(公告)号:US08379354B2

    公开(公告)日:2013-02-19

    申请号:US12269860

    申请日:2008-11-12

    IPC分类号: H02H9/00

    CPC分类号: H01L27/0262 H01L27/0251

    摘要: Self-triggered Multi-finger SCRs used in ESD protection circuitry capable of turning on all SCR fingers of the multi-finger SCRs include a first source, a second source, N SCR units, (N−1) diodes, and N resistors. Each of the N SCR units includes a first node, a second node coupled to the second source, and a trigger node. An nth diode of the (N−1) diodes is coupled between a first node of an nth SCR unit and a trigger node of an (n+1)th SCR unit. An nth resistor is coupled between the first node of the nth SCR unit and the first source, wherein n and N are integers. The (N−1) diodes can be replaced by directly coupled the first node of the nth SCR unit to the trigger node of the (n+1)th SCR unit when a trigger pulse is applied at the trigger node of a first SCR unit.

    摘要翻译: 能够接通多指SCR的所有SCR指状物的ESD保护电路中使用的自触发多指SCR包括第一源,第二源,N个SCR单元,(N-1)二极管和N个电阻器。 N个SCR单元中的每一个包括第一节点,耦合到第二源的第二节点和触发节点。 (N-1)二极管的第n个二极管耦合在第n个SCR单元的第一节点和第(n + 1)个SCR单元的触发节点之间。 第n个电阻耦合在第n个SCR单元的第一个节点和第一个源之间,其中n和N是整数。 当在第一SCR单元的触发节点处施加触发脉冲时,可以将第N个SCR单元的第一节点直接耦合到第(n + 1)个SCR单元的触发节点来代替(N-1) 。

    ESD protection circuit with merged triggering mechanism
    16.
    发明授权
    ESD protection circuit with merged triggering mechanism 有权
    具有合并触发机制的ESD保护电路

    公开(公告)号:US08243404B2

    公开(公告)日:2012-08-14

    申请号:US12543468

    申请日:2009-08-18

    IPC分类号: H02H3/22

    CPC分类号: H02H9/046

    摘要: An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device.

    摘要翻译: ESD保护电路具有合并的触发机制。 ESD保护电路包括:ESD检测电路,用于检测ESD电压以产生控制信号; 第一类ESD保护装置,用于输出第一触发电流; 第二类ESD保护装置,用于接收第二触发电流; 以及触发电路,用于根据控制信号构成导电路径,使得触发电路可以从第一类ESD保护装置接收第一触发电流,并将第二触发电流输出到第二类ESD保护装置。

    Polydiode structure for photo diode
    17.
    发明授权
    Polydiode structure for photo diode 有权
    光电二极管的多晶硅结构

    公开(公告)号:US08367457B2

    公开(公告)日:2013-02-05

    申请号:US13205017

    申请日:2011-08-08

    IPC分类号: H01L21/00

    摘要: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

    摘要翻译: 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底,形成在半导体衬底内部的阱区,形成在阱区上的电介质层和用于接收入射光信号的多晶硅层,形成 包括p型部分,n型部分和设置在p型和n型部分之间的未掺杂部分,其中阱区被偏置以控制多晶硅层以提供电信号 。

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    18.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权
    静电放电保护装置

    公开(公告)号:US20120146151A1

    公开(公告)日:2012-06-14

    申请号:US13040415

    申请日:2011-03-04

    IPC分类号: H01L23/62

    摘要: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

    摘要翻译: 公开了一种包括衬底,第一掺杂区域,第二掺杂区域和第三掺杂区域的静电放电(ESD)保护器件,栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中,包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上,位于第一和第二掺杂区之间,并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

    ESD detection circuit and related method thereof
    19.
    发明授权
    ESD detection circuit and related method thereof 有权
    ESD检测电路及其相关方法

    公开(公告)号:US07884617B2

    公开(公告)日:2011-02-08

    申请号:US12334496

    申请日:2008-12-14

    IPC分类号: H01H31/02

    CPC分类号: H02H9/046

    摘要: An electro-static discharge (ESD) detection circuit is provided. The ESD detection circuit includes: a first power pad for receiving a first supply voltage; a second power pad for receiving a second supply voltage; an RC circuit having an impedance component coupled between the first power pad and a first terminal and having an capacitive component coupled between the first terminal and a second terminal, wherein the second terminal is not directly connected to the second supply voltage; a trigger circuit couples to the first power pad, the second power pad, and the RC circuit, for generating an ESD trigger signal according to a voltage level at the first terminal and a voltage level at the second terminal, and a bias circuit coupled between the first power pad and the second power pad for providing a bias voltage to the second terminal.

    摘要翻译: 提供静电放电(ESD)检测电路。 ESD检测电路包括:用于接收第一电源电压的第一电源焊盘; 用于接收第二电源电压的第二电源焊盘; RC电路,其阻抗分量耦合在第一功率焊盘和第一端子之间,并具有耦合在第一端子和第二端子之间的电容部件,其中第二端子不直接连接到第二电源电压; 触发电路耦合到第一功率焊盘,第二功率焊盘和RC电路,用于根据第一端子处的电压电平和第二端子处的电压电平产生ESD触发信号,以及耦合在第二端子之间的偏置电路 所述第一功率垫和所述第二功率垫用于向所述第二端子提供偏置电压。

    Electrostatic discharge protection device and related circuit
    20.
    发明授权
    Electrostatic discharge protection device and related circuit 有权
    静电放电保护装置及相关电路

    公开(公告)号:US07880195B2

    公开(公告)日:2011-02-01

    申请号:US12329636

    申请日:2008-12-08

    IPC分类号: H01L29/66

    CPC分类号: H01L27/0262

    摘要: An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

    摘要翻译: ESD保护装置包括P型衬底,设置在P型衬底中的第一衬底触发的可控硅整流器(STSCR)和设置在P型衬底中的第二STSCR。 第一STSCR包括第一N阱,第一P阱,第一N +扩散区,第一P +扩散区和第一触发节点。 第二STSCR包括电连接到第一N阱的第二N阱,电连接到第一P阱的第二P阱,电连接到第一P +扩散区的第二N +扩散区,第二P +扩散 电连接到第一N +扩散区域的区域和第二触发器节点。 可以减小集成电路的布局区域和引脚到针脚ESD电流路径。