公开(公告)号：US08716801B2

公开(公告)日：2014-05-06

申请号：US13353235

申请日：2012-01-18

申请人： Lu-An Chen ,  Chang-Tzu Wang ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Chang-Tzu Wang ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/87

摘要： Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.

摘要翻译： 提供了一种金属氧化物半导体器件，其包括衬底，栅极，第一类型的第一重掺杂区域，第一类型漂移区域，第二类型第一重掺杂区域，接触区，第一电极和第二 电极。 栅极设置在基板上。 第一类型的第一重掺杂区域设置在栅极侧的衬底中。 第一类漂移区域设置在栅极另一侧的衬底中。 第二类型的第一重掺杂区域设置在第一类漂移区域中。 触点电连接到第二类型的第一重掺杂区域。 触点是与第一型漂移区上的栅极最接近的接触点。 第一电极电连接到触点，并且第二电极电连接到第一类型的第一重掺杂区域和栅极。

公开(公告)号：US20130113045A1

公开(公告)日：2013-05-09

申请号：US13290399

申请日：2011-11-07

申请人： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

发明人： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

摘要： An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

摘要翻译： 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

公开(公告)号：US20130107402A1

公开(公告)日：2013-05-02

申请号：US13281456

申请日：2011-10-26

申请人： Chang-Tzu Wang ,  Tien-Hao Tang

发明人： Chang-Tzu Wang ,  Tien-Hao Tang

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic protection circuit includes a strained transistor array, an unstrained transistor, and a control circuit. The strained transistor array has a first end electrically connected to a bias terminal. The unstrained transistor has a first end electrically connected to the bias terminal. The control circuit is electrically connected to a second end of the strained transistor array, a second end of the unstrained transistor and a ground terminal. The control circuit controls impedance between the second end of the strained transistor array and the ground terminal according to current flowing through the unstrained transistor. The electrostatic protection circuit is capable of preventing latch-up effect.

摘要翻译： 静电保护电路包括应变晶体管阵列，未应变晶体管和控制电路。 应变晶体管阵列具有电连接到偏置端子的第一端。 所述非限制晶体管具有电连接到所述偏置端子的第一端。 控制电路电连接到应变晶体管阵列的第二端，未应变晶体管的第二端和接地端子。 控制电路根据流过未应变晶体管的电流来控制应变晶体管阵列的第二端和接地端子之间的阻抗。 静电保护电路能够防止闩锁效应。

公开(公告)号：US20120170160A1

公开(公告)日：2012-07-05

申请号：US12981521

申请日：2010-12-30

申请人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

发明人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC分类号： H02H9/00

CPC分类号： H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

摘要： The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

摘要翻译： ESD保护电路电连接在第一电力轨道和第二电力轨道之间，并且包括ESD保护装置，电连接在ESD保护装置和第一电力轨道之间的开关装置和电连接在第一电力轨道之间的低通滤波器 第一电力轨道和第一开关装置。 ESD保护器件包括BJT和电连接在BJT的基极和第一电源轨之间的第一电阻器。 当不发生ESD事件时，基极的电位大于或等于BJT发射极的电位。 当ESD事件发生时，基极的电位小于发射极的电位。

公开(公告)号：US20110193170A1

公开(公告)日：2011-08-11

申请号：US12704065

申请日：2010-02-11

申请人： Chang-Tzu WANG ,  Tien-Hao TANG

发明人： Chang-Tzu WANG ,  Tien-Hao TANG

IPC分类号： H01L23/60

CPC分类号： H01L27/0274 ,  H01L27/0277

摘要： An ESD clamping device comprises a plurality of fingers each comprising a source region of first conductivity type formed in a substrate of second conductivity type, a drain region of said first conductivity type formed in the substrate, and a gate formed over the substrate and between the source and drain regions. At least one of the fingers each has an ESD implantation region formed in the substrate and partially underlying the drain region of the finger, the ESD implantation region being a heavily doped region of said second conductivity type. Furthermore, at least one of the fingers has a gate extension portion projecting from the gate and demarcating an additional region in at least the drain region of the finger, the additional region of said second conductivity type being electrically connected to at least one of the gate and the substrate of each of the fingers.

摘要翻译： ESD钳位装置包括多个指状物，每个指状物包括形成在第二导电类型的衬底中的第一导电类型的源极区域，形成在衬底中的所述第一导电类型的漏极区域，以及形成在衬底上方之间的栅极 源极和漏极区域。 每个手指中的至少一个具有形成在衬底中并部分地位于手指的漏极区域的ESD注入区域，ESD注入区域是所述第二导电类型的重掺杂区域。 此外，指状物中的至少一个具有从栅极突出并且限定手指的至少漏极区域中的附加区域的栅极延伸部分，所述第二导电类型的附加区域电连接到栅极的至少一个 和每个手指的基板。

公开(公告)号：US07880195B2

公开(公告)日：2011-02-01

申请号：US12329636

申请日：2008-12-08

申请人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Chang-Tzu Wang

发明人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Chang-Tzu Wang

IPC分类号： H01L29/66

CPC分类号： H01L27/0262

摘要： An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

摘要翻译： ESD保护装置包括P型衬底，设置在P型衬底中的第一衬底触发的可控硅整流器（STSCR）和设置在P型衬底中的第二STSCR。 第一STSCR包括第一N阱，第一P阱，第一N +扩散区，第一P +扩散区和第一触发节点。 第二STSCR包括电连接到第一N阱的第二N阱，电连接到第一P阱的第二P阱，电连接到第一P +扩散区的第二N +扩散区，第二P +扩散 电连接到第一N +扩散区域的区域和第二触发器节点。 可以减小集成电路的布局区域和引脚到针脚ESD电流路径。

公开(公告)号：US20100140659A1

公开(公告)日：2010-06-10

申请号：US12329636

申请日：2008-12-08

申请人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Chang-Tzu Wang

发明人： Ming-Dou Ker ,  Yuan-Wen Hsiao ,  Chang-Tzu Wang

IPC分类号： H01L29/74

CPC分类号： H01L27/0262

摘要： An ESD protection device comprises a P-type substrate, a first substrate-triggered silicon controlled rectifiers (STSCR) disposed in the P-type substrate and a second STSCR disposed in the P-type substrate. The first STSCR comprises a first N-well, a first P-well, a first N+ diffusion region, a first P+ diffusion region, and a first trigger node. The second STSCR comprises a second N-well electrically connected to the first N-well, a second P-well electrically connected to the first P-well, a second N+ diffusion region electrically connected to the first P+ diffusion region, a second P+ diffusion region electrically connected to the first N+ diffusion region, and a second trigger node. A layout area of an integrated circuit and a pin-to-pin ESD current path can be reduced.

摘要翻译： ESD保护装置包括P型衬底，设置在P型衬底中的第一衬底触发的可控硅整流器（STSCR）和设置在P型衬底中的第二STSCR。 第一STSCR包括第一N阱，第一P阱，第一N +扩散区，第一P +扩散区和第一触发节点。 第二STSCR包括电连接到第一N阱的第二N阱，电连接到第一P阱的第二P阱，电连接到第一P +扩散区的第二N +扩散区，第二P +扩散 电连接到第一N +扩散区域的区域和第二触发器节点。 可以减小集成电路的布局区域和引脚到针脚ESD电流路径。

公开(公告)号：US20100118454A1

公开(公告)日：2010-05-13

申请号：US12269860

申请日：2008-11-12

申请人： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

发明人： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

IPC分类号： H02H7/00

CPC分类号： H01L27/0262 ,  H01L27/0251

摘要： Self-triggered Multi-finger SCRs used in ESD protection circuitry capable of turning on all SCR fingers of the multi-finger SCRs include a first source, a second source, N SCR units, (N−1) diodes, and N resistors. Each of the N SCR units includes a first node, a second node coupled to the second source, and a trigger node. An nth diode of the (N−1) diodes is coupled between a first node of an nth SCR unit and a trigger node of an (n+1)th SCR unit. An nth resistor is coupled between the first node of the nth SCR unit and the first source, wherein n and N are integers. The (N−1) diodes can be replaced by directly coupled the first node of the nth SCR unit to the trigger node of the (n+1)th SCR unit when a trigger pulse is applied at the trigger node of a first SCR unit.

摘要翻译： 能够接通多指SCR的所有SCR指状物的ESD保护电路中使用的自触发多指SCR包括第一源，第二源，N个SCR单元，（N-1）二极管和N个电阻器。 N个SCR单元中的每一个包括第一节点，耦合到第二源的第二节点和触发节点。 （N-1）二极管的第n个二极管耦合在第n个SCR单元的第一节点和第（n + 1）个SCR单元的触发节点之间。 第n个电阻耦合在第n个SCR单元的第一个节点和第一个源之间，其中n和N是整数。 当在第一SCR单元的触发节点处施加触发脉冲时，可以将第N个SCR单元的第一节点直接耦合到第（n + 1）个SCR单元的触发节点来代替（N-1） 。

公开(公告)号：US08963202B2

公开(公告)日：2015-02-24

申请号：US13369455

申请日：2012-02-09

申请人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

发明人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/87

摘要： A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.

摘要翻译： 半导体ESD保护装置包括基板; 第一掺杂阱，其设置在所述衬底中并且具有第一导电性; 具有第一导电性的第一掺杂区域设置在第一掺杂阱中; 第二掺杂区域，具有设置在第一掺杂阱中的第二导电体; 以及设置在所述衬底中的外延层，其中所述外延层具有具有所述第一导电性的第三掺杂区域和具有第二导电性的第四掺杂区域彼此分离。 由此在第一掺杂区，第一掺杂阱和第三掺杂区之间形成第一双极结型晶体管（BJT）等效电路; 在第二掺杂区，第一掺杂阱和第四掺杂区之间形成第二BJT等效电路; 并且第一BJT等效电路和第二BJT等效电路具有不同的多数载波。

公开(公告)号：US08525265B2

公开(公告)日：2013-09-03

申请号：US12705339

申请日：2010-02-12

申请人： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

发明人： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

IPC分类号： H01L23/62

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.