公开(公告)号：US08507946B2

公开(公告)日：2013-08-13

申请号：US13040415

申请日：2011-03-04

申请人： Yeh-Jen Huang ,  Yeh-Ning Jou ,  Ming-Dou Ker ,  Wen-Yi Chen ,  Chia-Wei Hung ,  Hwa-Chyi Chiou

发明人： Yeh-Jen Huang ,  Yeh-Ning Jou ,  Ming-Dou Ker ,  Wen-Yi Chen ,  Chia-Wei Hung ,  Hwa-Chyi Chiou

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L23/62

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

摘要翻译： 公开了一种包括衬底，第一掺杂区域，第二掺杂区域和第三掺杂区域的静电放电（ESD）保护器件，栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中，包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上，位于第一和第二掺杂区之间，并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

公开(公告)号：US20120146151A1

公开(公告)日：2012-06-14

申请号：US13040415

申请日：2011-03-04

申请人： Yeh-Jen HUANG ,  Yeh-Ning Jou ,  Ming-Dou Ker ,  Wen-Yi Chen ,  Chia-Wei Hung ,  Hwa-Chyi Chiou

发明人： Yeh-Jen HUANG ,  Yeh-Ning Jou ,  Ming-Dou Ker ,  Wen-Yi Chen ,  Chia-Wei Hung ,  Hwa-Chyi Chiou

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

摘要翻译： 公开了一种包括衬底，第一掺杂区域，第二掺杂区域和第三掺杂区域的静电放电（ESD）保护器件，栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中，包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上，位于第一和第二掺杂区之间，并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

公开(公告)号：US08278736B2

公开(公告)日：2012-10-02

申请号：US12875217

申请日：2010-09-03

申请人： Yeh-Ning Jou ,  Chia-Wei Hung ,  Shu-Ling Chang ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang

发明人： Yeh-Ning Jou ,  Chia-Wei Hung ,  Shu-Ling Chang ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang

IPC分类号： H01L29/739 ,  H01L23/60

CPC分类号： H01L27/0259 ,  H01L27/0274

摘要： An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

摘要翻译： 提供耦合在第一电力线和第二电力线之间的静电放电保护装置。 在P型阱中形成第一N型掺杂区。 在第一N型掺杂区域中形成第一P型掺杂区域。 第二P型掺杂区域包括第一部分和第二部分。 第二P型掺杂区的第一部分形成在第一N型掺杂区中。 第二P型掺杂区的第二部分形成在第一N型掺杂区的外部。 在第二P型掺杂区域的第一部分中形成第二N型掺杂区域。 第一P型掺杂区域，第一N型掺杂区域，第二P型掺杂区域和第二N型掺杂区域构成绝缘栅双极晶体管（IGBT）。

公开(公告)号：US08278715B2

公开(公告)日：2012-10-02

申请号：US13019846

申请日：2011-02-02

申请人： Yeh-Ning Jou ,  Chia-Wei Hung ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang ,  Shu-Ling Chang

发明人： Yeh-Ning Jou ,  Chia-Wei Hung ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang ,  Shu-Ling Chang

IPC分类号： H01L23/62 ,  H01L29/772

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

摘要翻译： 公开了ESD保护结构。 衬底包括第一导电类型。 在基板中形成第一扩散区。 第一掺杂区形成在第一扩散区中。 在第一扩散区域中形成第二掺杂区域。 在衬底中形成第三掺杂区。 第一隔离区形成在衬底中，覆盖第一扩散区的一部分并位于第二和第三掺杂区之间。 在衬底中形成第四掺杂区。 当第一掺杂区耦合到第一电源线并且第三和第四掺杂区耦合到第二电源线时，ESD电流可以从第一电力线释放到第二电力线。 在释放ESD电流期间，第二掺杂区域不与第一电力线电连接。

公开(公告)号：US08008726B2

公开(公告)日：2011-08-30

申请号：US12887463

申请日：2010-09-21

申请人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

发明人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

IPC分类号： H01L23/60

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

摘要翻译： 提出了Trig调制静电放电（ESD）保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱（HVNW）区域。 在HVNW区域中形成NDD区域，第一P体区域和第二P体区域，其中，第一P体区域与第二P体区域以预定距离分离，并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间，第二栅极设置在N +掺杂区域和P +掺杂区域之间。

公开(公告)号：US07821070B2

公开(公告)日：2010-10-26

申请号：US12265603

申请日：2008-11-05

申请人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

发明人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

IPC分类号： H01L23/60

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

摘要翻译： 提出了Trig调制静电放电（ESD）保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱（HVNW）区域。 在HVNW区域中形成NDD区域，第一P体区域和第二P体区域，其中，第一P体区域与第二P体区域以预定距离分离，并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间，第二栅极设置在N +掺杂区域和P +掺杂区域之间。

公开(公告)号：US20050179087A1

公开(公告)日：2005-08-18

申请号：US10977023

申请日：2004-11-01

申请人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

发明人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/7835

摘要： An ESD protection device. The ESD protection device is incorporated with a gap structure in a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor, isolating a doped region and a field oxide region. When a parasitical semiconductor controlled rectifier (SCR) of LDMOS is turned off, ESD current is discharged distributively through several discharge paths, avoiding ESD current focus in a signal narrow discharge path and the danger therefrom.

摘要翻译： ESD保护装置。 ESD保护装置在横向扩散的金属氧化物半导体（LDMOS）场效应晶体管中结合有间隙结构，隔离掺杂区域和场氧化物区域。 当LDMOS的寄生半导体可控整流器（SCR）关闭时，ESD电流通过多个放电路径分布放电，避免信号窄放电路径中的ESD电流聚焦及其危险。

公开(公告)号：US20110012204A1

公开(公告)日：2011-01-20

申请号：US12887463

申请日：2010-09-21

申请人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

发明人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

IPC分类号： H01L27/092

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

摘要翻译： 提出了Trig调制静电放电（ESD）保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱（HVNW）区域。 在HVNW区域中形成NDD区域，第一P体区域和第二P体区域，其中，第一P体区域与第二P体区域以预定距离分离，并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间，第二栅极设置在N +掺杂区域和P +掺杂区域之间。

公开(公告)号：US20090261417A1

公开(公告)日：2009-10-22

申请号：US12265603

申请日：2008-11-05

申请人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

发明人： Yeh-Ning Jou ,  Hwa-Chyi Chiou

IPC分类号： H01L27/092

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

摘要翻译： 提出了Trig调制静电放电（ESD）保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱（HVNW）区域。 在HVNW区域中形成NDD区域，第一P体区域和第二P体区域，其中，第一P体区域与第二P体区域以预定距离分离，并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间，第二栅极设置在N +掺杂区域和P +掺杂区域之间。

公开(公告)号：US07098522B2

公开(公告)日：2006-08-29

申请号：US10956063

申请日：2004-10-04

申请人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

发明人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC分类号： H01L29/00

CPC分类号： H01L27/0262

摘要： A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

摘要翻译： 高压设备。 在ESD保护器件中将高电压MOS晶体管施加到其中添加掺杂区域的结构，产生具有更短放电路径的寄生半导体可控整流器（SCR），使得SCR具有更快的响应增强ESD保护。