公开(公告)号：US09935786B2

公开(公告)日：2018-04-03

申请号：US15063124

申请日：2016-03-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart ,  John Bruce Bowlerwell ,  Michael Page ,  Alastair Boomer

IPC: H04L12/40 ,  H04L5/14 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4027 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016 ,  H04L5/1476

Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

公开(公告)号：US09836274B2

公开(公告)日：2017-12-05

申请号：US14928295

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: G06F17/00 ,  G06F3/16 ,  G06F13/38

CPC classification number: G06F3/165 ,  G06F13/385

Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronization data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronization data pattern comprises first signal level transitions on the at least one wire, synchronized to a master transmission clock. At second times, a second synchronization data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronization data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory. In the device, timings of said second signal level transitions as received at said device are determined relative to the master transmission clock, and timing delay control data based on said determination is transmitted from the device to the accessory. In the accessory, the timing delay control data is received, and the stored delay value is updated based on the timing delay control data.

公开(公告)号：US10298379B2

公开(公告)日：2019-05-21

申请号：US15840592

申请日：2017-12-13

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: H04L5/16 ,  H04L7/00

Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

公开(公告)号：US10042796B2

公开(公告)日：2018-08-07

申请号：US14928430

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: G06F13/42 ,  G06F13/362 ,  G06F13/38 ,  G06F13/40

Abstract: An audio system comprises a master device; a slave device; and a wired connection, suitable for connecting the master device and the slave device, and having at least two wires. In order to compensate for a round-trip transmission delay, a method comprises: transmitting a master clock signal on a first wire of the two wires, from said master device to said slave device; transmitting a synchronisation data pattern on a second wire of the two wires, from said slave device to said master device, wherein said synchronisation data pattern comprises signal level transitions at timings that are set based on a delay value stored in said slave device; in said master device, determining timings of said signal level transitions as received at said master device; transmitting, on the second wire, from said master device to said slave device, timing delay control data based on said determination; and in said slave device, receiving said timing delay control data; and updating said stored delay value based on said timing delay control data.

公开(公告)号：US10027514B2

公开(公告)日：2018-07-17

申请号：US14928766

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart ,  Bhupendra Singh Manola

IPC: H04L25/02 ,  H04L5/16 ,  H04L5/14 ,  H04B3/30

Abstract: A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires. The first module includes a first detector for obtaining first output data based on voltages across the resistors resulting from the signal current injected by the current generation circuitry of the second module; and the second module includes a second detector for obtaining second output data based on differential signal imposed by the signal generation circuitry of the first module.

公开(公告)号：US09853804B2

公开(公告)日：2017-12-26

申请号：US14928179

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: H04L5/16 ,  H04L7/00

CPC classification number: H04L5/16 ,  H04L7/0008

Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

公开(公告)号：US20160337113A1

公开(公告)日：2016-11-17

申请号：US14928382

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: H04L5/16 ,  H04B3/02 ,  H04L7/00 ,  H04L1/00

CPC classification number: H04L5/16 ,  H04B3/02 ,  H04L1/0061 ,  H04L7/0008

Abstract: A method is used for transferring data over a half-duplex wired communications link, wherein the wired communications link comprises first and second wires. The method comprises, in each of a plurality of frames: transferring a clock signal on the first wire in a first direction; transferring first payload data on the second wire in the first direction; transferring second payload data on the second wire in a second direction opposite to the first direction; and transferring control data on the second wire, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

Abstract translation: 一种方法用于通过半双工有线通信链路传送数据，其中有线通信链路包括第一和第二线。 该方法包括在多个帧中的每一个中：在第一方向上在第一线上传送时钟信号; 在第一方向上将第一有效载荷数据传送到第二线上; 在与第一方向相反的第二方向上将第二有效载荷数据传送到第二线上; 以及在所述第二线路上传送控制数据，其中所述帧的格式使得不管所述控制数据是在所述第一方向还是在所述第二方向上传送，所述数据传送方向只有一对反转 在每一帧。

公开(公告)号：US20160335211A1

公开(公告)日：2016-11-17

申请号：US14928430

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: G06F13/362 ,  G06F13/40

CPC classification number: G06F13/3625 ,  G06F13/385 ,  G06F13/4068

Abstract: An audio system comprises a master device; a slave device; and a wired connection, suitable for connecting the master device and the slave device, and having at least two wires. In order to compensate for a round-trip transmission delay, a method comprises: transmitting a master clock signal on a first wire of the two wires, from said master device to said slave device; transmitting a synchronisation data pattern on a second wire of the two wires, from said slave device to said master device, wherein said synchronisation data pattern comprises signal level transitions at timings that are set based on a delay value stored in said slave device; in said master device, determining timings of said signal level transitions as received at said master device; transmitting, on the second wire, from said master device to said slave device, timing delay control data based on said determination; and in said slave device, receiving said timing delay control data; and updating said stored delay value based on said timing delay control data.

Abstract translation: 音频系统包括主设备; 一个从设备; 以及适于连接主设备和从设备的有线连接，并且具有至少两根电线。 为了补偿往返传输延迟，一种方法包括：在所述主设备到所述从设备的两条线路的第一线上发送主时钟信号; 在所述从设备到所述主设备的两条线路的第二线路上发送同步数据模式，其中所述同步数据模式包括基于存储在所述从设备中的延迟值设置的定时的信号电平转换; 在所述主设备中，确定在所述主设备处接收到的所述信号电平转换的定时; 在所述第二配线上从所述主设备向所述从设备发送基于所述确定的定时延迟控制数据; 并且在所述从设备中接收所述定时延迟控制数据; 以及基于所述定时延迟控制数据更新所述存储的延迟值。

公开(公告)号：US20160154622A1

公开(公告)日：2016-06-02

申请号：US14928295

申请日：2015-10-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Willem Zwart

IPC: G06F3/16

CPC classification number: G06F3/165 ,  G06F13/385

Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory. In the device, timings of said second signal level transitions as received at said device are determined relative to the master transmission clock, and timing delay control data based on said determination is transmitted from the device to the accessory. In the accessory, the timing delay control data is received, and the stored delay value is updated based on the timing delay control data.

Abstract translation: 一种补偿音频系统中的往返传输延迟的方法，包括：便携式通信设备; 音响配件; 以及适于连接便携式通信设备和音频附件的电缆，其具有至少一根电线并且可从便携式通信设备和音频附件中的至少一个拆卸。 在第一时间，第一同步数据模式在所述至少一条线路上从所述设备发送到所述附件，其中所述第一同步数据模式包括与主传输时钟同步的至少一条线上的第一信号电平转换。 在第二次，在所述附件至所述装置的至少一根导线上发送第二同步数据模式，其中所述第二同步数据模式包括基于存储在所述附件中的延迟值设置的定时的第二信号电平转换。 在设备中，相对于主传输时钟确定在所述设备处接收到的所述第二信号电平转换的定时，并且基于所述确定的定时延迟控制数据从设备传输到附件。 在附件中，接收定时延迟控制数据，并且基于定时延迟控制数据来更新所存储的延迟值。

公开(公告)号：US10567214B2

公开(公告)日：2020-02-18

申请号：US15966631

申请日：2018-04-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Alastair Mark Boomer ,  Erich Paul Zwyssig ,  Gavin Alexander Waite ,  Willem Zwart

IPC: H04L12/24 ,  H04L7/00 ,  H04J3/06

Abstract: Communication circuitry, comprising: N communication nodes being clock-candidate nodes, where N≥2; N communication units for communication using respective communication protocols, and connected or connectable to receive respective clock signals for communication under their respective communication protocols via respective said clock-candidate nodes; and a control unit configured, in a decision operation, to monitor the clock-candidate nodes and decide which of the communication protocols is in use dependent on at which of the clock-candidate nodes a received clock signal is detected, wherein at least one said communication unit is connected or connectable to receive and/or transmit data under its respective communication protocol via at least one said clock-candidate node other than the clock-candidate node via which that communication unit is to receive its respective clock signal.