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公开(公告)号：US11023821B2
公开(公告)日：2021-06-01
申请号：US15881260
申请日：2018-01-26
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Kelly T. R. Boothby , Andrew D. King
Abstract: A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.
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12.发明授权公开(公告)号：US12118197B2
公开(公告)日：2024-10-15
申请号：US18205379
申请日：2023-06-02
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Fiona L. Hanington , Alexander Condello , William W. Bernoudy , Melody C. Wong , Aidan P. Roy , Kelly T. R. Boothby , Edward D. Dahl
IPC: G06F3/04847 , G06F3/04817 , G06F16/901 , G06N10/00 , G06T11/20
CPC classification number: G06F3/04847 , G06F3/04817 , G06F16/9024 , G06N10/00 , G06T11/206 , G06T2200/24
Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
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公开(公告)号：US20240338584A1
公开(公告)日：2024-10-10
申请号：US18293559
申请日：2022-07-27
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: Topologies for analog processors may include cells comprising at least portions of qubits and couplers. Qubits and couplers may be shared among or extend across multiple cells. A cell may include four sets of partial qubits, and partial qubits may form whole qubits with partial qubits in adjacent cells. First and second sets of partial qubits may include partial qubits that extend substantially parallel to one another and along a first direction. Third and fourth sets may include partial qubits that extend substantially parallel to one another and along a second direction. Each partial qubit in the first and second sets may cross, and be substantially orthogonal to, at least one partial qubit from each of the third and fourth sets. A cell may include first and second sets of intra-cell couplers, and partial couplers that form inter-cell couplers with partial couplers in adjacent cells.
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公开(公告)号：US12033033B2
公开(公告)日：2024-07-09
申请号：US17607278
申请日：2020-06-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
CPC classification number: G06N10/40 , H10N60/12 , H10N60/805
Abstract: A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
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15.发明公开公开(公告)号：US20230385668A1
公开(公告)日：2023-11-30
申请号：US18203880
申请日：2023-05-31
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Aidan P. Roy , Fabian A. Chudak , Zhengbing Bian , William G. Macready , Robert B. Israel , Kelly T. R. Boothby , Sheir Yarkoni , Yanbo Xue , Dmytro Korenkevych
IPC: G06N10/00
CPC classification number: G06N10/00
Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
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Patent Agency Ranking
公开(公告)号：US20230169378A1
公开(公告)日：2023-06-01
申请号：US17988250
申请日：2022-11-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： James A. King , William W. Bernoudy , Kelly T. R. Boothby , Pau Farré Pérez
IPC: G06N10/00 , G06F17/18 , G06F18/21 , G06F18/23213
CPC classification number: G06N10/00 , G06F17/18 , G06F18/217 , G06F18/23213
Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
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17.发明公开公开(公告)号：US20230143506A1
公开(公告)日：2023-05-11
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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18.发明授权公开(公告)号：US11409426B2
公开(公告)日：2022-08-09
申请号：US17182975
申请日：2021-02-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Fiona L. Hanington , Alexander Condello , William W. Bernoudy , Melody C. Wong , Aidan P. Roy , Kelly T. R. Boothby , Edward D. Dahl
IPC: G06F3/048 , G06F3/04847 , G06N10/00 , G06T11/20 , G06F3/04817 , G06F16/901
Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
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公开(公告)号：US10748079B2
公开(公告)日：2020-08-18
申请号：US16694693
申请日：2019-11-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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20.发明申请公开(公告)号：US20200111016A1
公开(公告)日：2020-04-09
申请号：US16694693
申请日：2019-11-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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