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    SYSTEMS AND METHODS FOR SIMULATING A QUANTUM PROCESSOR
    1.
    发明申请
    SYSTEMS AND METHODS FOR SIMULATING A QUANTUM PROCESSOR 有权

    公开(公告)号：US20220253740A1

    公开(公告)日：2022-08-11

    申请号：US17617388

    申请日：2020-07-10

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mark W. Johnson ,  Mauricio Reis Filho ,  Mark H. Volkmann ,  Ilya V. Perminov ,  Paul I. Bunyk

    IPC: G06N10/20

    Abstract: A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.

    Quantum processor with instance programmable qubit connectivity
    3.
    发明授权
    Quantum processor with instance programmable qubit connectivity 有权

    公开(公告)号：US09710758B2

    公开(公告)日：2017-07-18

    申请号：US14691268

    申请日：2015-04-20

    Applicant: D-Wave Systems Inc.

    Inventor： Paul I. Bunyk ,  Mohammad H. S. Amin ,  Richard G. Harris ,  Trevor Michael Lanting ,  Mark W. Johnson ,  Jeremy P. Hilton ,  Emile M. Hoskinson

    IPC: G06F15/82 ,  G06N99/00

    CPC classification number: G06N99/002 ,  G06F15/82

    Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.

    Systems and methods employing new evolution schedules in an analog computer with applications to determining isomorphic graphs and post-processing solutions
    6.
    发明授权
    Systems and methods employing new evolution schedules in an analog computer with applications to determining isomorphic graphs and post-processing solutions 有权

    公开(公告)号：US10769545B2

    公开(公告)日：2020-09-08

    申请号：US14734924

    申请日：2015-06-09

    Applicant: D-Wave Systems Inc.

    Inventor： Mohammad H.S. Amin ,  Mark W. Johnson

    IPC: G06F17/00 ,  G06N5/00 ,  G06N10/00

    Abstract: A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian.

    Systems and methods employing new evolution schedules in an analog computer with applications to determining isomorphic graphs and post-processing solutions
    7.
    发明授权
    Systems and methods employing new evolution schedules in an analog computer with applications to determining isomorphic graphs and post-processing solutions 有权

    公开(公告)号：US11995513B2

    公开(公告)日：2024-05-28

    申请号：US16936742

    申请日：2020-07-23

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. S. Amin ,  Mark W. Johnson

    IPC: G06N10/00

    CPC classification number: G06N10/00

    Abstract: A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian.

    QUANTUM PROCESSOR WITH INSTANCE PROGRAMMABLE QUBIT CONNECTIVITY
    9.
    发明申请
    QUANTUM PROCESSOR WITH INSTANCE PROGRAMMABLE QUBIT CONNECTIVITY 有权
    量子处理器具有可靠的可编程连接性

    公开(公告)号：US20160335558A1

    公开(公告)日：2016-11-17

    申请号：US14691268

    申请日：2015-04-20

    Applicant: D-Wave Systems Inc.

    Inventor： Paul I. Bunyk ,  Mohammad H.S. Amin ,  Richard G. Harris ,  Trevor Michael Lanting ,  Mark W. Johnson ,  Jeremy P. Hilton ,  Emile M. Hoskinson

    IPC: G06N99/00 ,  G06F15/82

    CPC classification number: G06N99/002 ,  G06F15/82

    Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.

    Abstract translation: 在量子处理器中，一些耦合器将给定的量子比特耦合到最近的相邻量子位（例如，在有序2D阵列中垂直和水平），其他耦合器耦合到下一个最近的相邻量子位（例如，在有序2D阵列中的对角线）。 耦合器可以包括半耦合器，以选择性地提供给定量子位与其他量子位之间的通信耦合，其可以是也可以不是最近的，或者甚至不是最近邻近的。 可调谐耦合器选择性地介入交流耦合。 控制系统可以在量子处理器上施加不同于“被设计”或“制造”的物理连接的连接。 拼版可以通过数字处理器处理工作或更新的工作图，映射或嵌入问题图。 可以从硬件和工作图的比较中创建一组排除量子位。 退火计划可以调整一个或多个量子位的相应的归一化电感，例如排除某些量子位。

    SYSTEMS AND METHODS FOR SUPERCONDUCTING INTEGRATED CIRCUITS
    10.
    发明申请
    SYSTEMS AND METHODS FOR SUPERCONDUCTING INTEGRATED CIRCUITS 有权
    超级集成电路系统与方法

    公开(公告)号：US20140228222A1

    公开(公告)日：2014-08-14

    申请号：US14255561

    申请日：2014-04-17

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Andrew J. Berkley ,  Mark W. Johnson ,  Paul I. Bunyk

    IPC: G06N99/00 ,  H01L23/532

    CPC classification number: G06N99/002 ,  B82Y10/00 ,  H01L23/53285 ,  H01L27/18 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

    Abstract translation: 超导集成电路可以包括具有内部感应耦合元件和外部感应耦合元件的磁通量变换器，该外部感应耦合元件沿其长度的至少一部分围绕内部感应耦合元件。 磁通变压器可以具有类似同轴的几何形状，使得第一感应耦合元件和第二感应耦合元件之间的互感与将第一内部感应耦合元件与第一外部电感耦合器分开的距离成亚线性比例 元件。 第一电感耦合元件和第二电感耦合元件中的至少一个可以耦合到超导可编程器件，例如超导量子位。

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