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公开(公告)号：US11874344B2
公开(公告)日：2024-01-16
申请号：US18082385
申请日：2022-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Andrew J. Berkley , Mark H. Volkmann , George E. G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , G06N10/00 , H10N60/12
CPC classification number: G01R33/0354 , G06N10/00 , H10N60/12
Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
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公开(公告)号：US20230204691A1
公开(公告)日：2023-06-29
申请号：US18082385
申请日：2022-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Andrew J. Berkley , Mark H. Volkmann , George E.G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , G06N10/00 , H10N60/12
CPC classification number: G01R33/0354 , G06N10/00 , H10N60/12
Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
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公开(公告)号：US11422958B2
公开(公告)日：2022-08-23
申请号：US16872595
申请日：2020-05-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Andrew J. Berkley , Christopher B. Rich
Abstract: A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
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公开(公告)号：US10938346B2
公开(公告)日：2021-03-02
申请号：US15572731
申请日：2016-05-11
Applicant: D-Wave Systems Inc.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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公开(公告)号：US20190305206A1
公开(公告)日：2019-10-03
申请号：US16380751
申请日：2019-04-10
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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Patent Agency Ranking
公开(公告)号：US10290798B2
公开(公告)日：2019-05-14
申请号：US15438296
申请日：2017-02-21
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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公开(公告)号：US10140248B2
公开(公告)日：2018-11-27
申请号：US15635735
申请日：2017-06-28
Applicant: D-Wave Systems Inc.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices. A method of determining a result of a computational problem using an analog processor includes receiving at a first digital computer, including a digital processor, an instance of the computational problem defined over an input graph, wherein the input graph is non-planar; and determining a mapping of the instance of the computational problem onto the analog processor, by the digital processor.
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公开(公告)号：US20170300454A1
公开(公告)日：2017-10-19
申请号：US15635735
申请日：2017-06-28
Applicant: D-Wave Systems Inc.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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公开(公告)号：US20140223224A1
公开(公告)日：2014-08-07
申请号：US14173101
申请日：2014-02-05
Applicant: D-Wave Systems Inc.
Inventor： Andrew J. Berkley
IPC: G06F11/07
CPC classification number: G06F11/0724 , G06F11/10 , G06F11/1492 , G06N99/002
Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.
Abstract translation: 通过实现复制编码方案，减少绝热和/或噪声对绝热量子计算和量子退火的影响。 相同问题的多个实例被映射到量子位的相应子集和量子处理器的耦合器件。 在不同实例的量子位之间存在耦合的情况下，多个实例同时进化。 还描述了适于促进复制编码的量子处理器体系结构。
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10.发明授权公开(公告)号：US11730066B2
公开(公告)日：2023-08-15
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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