公开(公告)号：US10789540B2

公开(公告)日：2020-09-29

申请号：US15487295

申请日：2017-04-13

Applicant: D-Wave Systems Inc.

Inventor： Andrew D. King ,  Robert B. Israel ,  Paul I. Bunyk ,  Kelly T. R. Boothby ,  Steven P. Reinhardt ,  Aidan P. Roy ,  James A. King ,  Trevor M. Lanting ,  Abraham J. Evert

IPC: G06N10/00 ,  G06N3/12

Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.

公开(公告)号：US11880741B2

公开(公告)日：2024-01-23

申请号：US16988232

申请日：2020-08-07

Applicant: D-WAVE SYSTEMS INC.

Inventor： Robert B. Israel ,  Trevor M. Lanting ,  Andrew D. King

IPC: G06N10/00 ,  G06N20/00 ,  G06N3/126

CPC classification number: G06N10/00 ,  G06N3/126 ,  G06N20/00

Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.

公开(公告)号：US11494683B2

公开(公告)日：2022-11-08

申请号：US16955526

申请日：2018-12-19

Applicant: D-Wave Systems Inc.

Inventor： Mohammad H. Amin ,  Paul I. Bunyk ,  Trevor M. Lanting ,  Chunqing Deng ,  Anatoly Smirnov ,  Kelly T. R. Boothby ,  Emile M. Hoskinson ,  Christopher B. Rich

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/22

Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δeff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).

公开(公告)号：US11100418B2

公开(公告)日：2021-08-24

申请号：US16275816

申请日：2019-02-14

Applicant: D-WAVE SYSTEMS INC.

Inventor： Paul I. Bunyk ,  James King ,  Murray C. Thom ,  Mohammad H. Amin ,  Anatoly Yu Smirnov ,  Sheir Yarkoni ,  Trevor M. Lanting ,  Andrew D. King ,  Kelly T. R. Boothby

IPC: G06N10/00 ,  G06F11/07

Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.

公开(公告)号：US20200152851A1

公开(公告)日：2020-05-14

申请号：US16681431

申请日：2019-11-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/24 ,  H01L39/22

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US20170300817A1

公开(公告)日：2017-10-19

申请号：US15487295

申请日：2017-04-13

Applicant: D-Wave Systems Inc.

Inventor： Andrew D. King ,  Robert B. Israel ,  Paul I. Bunyk ,  Tomas J. Boothby ,  Steven P. Reinhardt ,  Aidan P. Roy ,  James A. King ,  Trevor M. Lanting ,  Abraham J. Evert

IPC: G06N5/02 ,  G06N99/00

CPC classification number: G06N10/00 ,  G06N3/126

Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.