公开(公告)号：US20200152851A1

公开(公告)日：2020-05-14

申请号：US16681431

申请日：2019-11-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/24 ,  H01L39/22

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US20220263007A1

公开(公告)日：2022-08-18

申请号：US17681303

申请日：2022-02-25

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US20210384406A1

公开(公告)日：2021-12-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/18 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11957065B2

公开(公告)日：2024-04-09

申请号：US17321819

申请日：2021-05-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H10N60/01 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N60/85 ,  H10N69/00

CPC classification number: H10N60/0156 ,  H01L21/76891 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53285 ,  H10N60/85 ,  H10N69/00

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

公开(公告)号：US11856871B2

公开(公告)日：2023-12-26

申请号：US17681303

申请日：2022-02-25

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  H10N60/80 ,  G06N10/00 ,  H10N60/12 ,  H10N60/01 ,  H10N69/00

CPC classification number: H10N60/805 ,  G06N10/00 ,  H10N60/0156 ,  H10N60/0912 ,  H10N60/12 ,  H10N69/00

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US11038095B2

公开(公告)日：2021-06-15

申请号：US16481788

申请日：2018-01-31

Applicant: D-WAVE SYSTEMS INC.

Inventor： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC: H01L27/18 ,  H01L39/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L39/12

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.