公开(公告)号：US12035640B2

公开(公告)日：2024-07-09

申请号：US17330037

申请日：2021-05-25

申请人： D-WAVE SYSTEMS INC.

发明人： Richard G. Harris ,  Andrew J. Berkley ,  Jan Johansson ,  Mark Johnson ,  Mohammad Amin ,  Paul I. Bunyk

IPC分类号： H10N60/12 ,  B82Y10/00 ,  G06N10/40 ,  G06N10/70 ,  H03K19/195 ,  H10N69/00

CPC分类号： H10N60/12 ,  B82Y10/00 ,  G06N10/40 ,  G06N10/70 ,  H03K19/195 ,  H03K19/1954 ,  H10N69/00

摘要： Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

公开(公告)号：US20240070510A1

公开(公告)日：2024-02-29

申请号：US18272235

申请日：2022-01-11

申请人： D-WAVE SYSTEMS INC.

发明人： Min Jan Tsai ,  Colin C. Enderud ,  Reza Molavi ,  Paul I. Bunyk

IPC分类号： G06N10/40 ,  H03M1/66

CPC分类号： G06N10/40 ,  H03M1/66

摘要： Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.

公开(公告)号：US11494683B2

公开(公告)日：2022-11-08

申请号：US16955526

申请日：2018-12-19

申请人： D-Wave Systems Inc.

发明人： Mohammad H. Amin ,  Paul I. Bunyk ,  Trevor M. Lanting ,  Chunqing Deng ,  Anatoly Smirnov ,  Kelly T. R. Boothby ,  Emile M. Hoskinson ,  Christopher B. Rich

IPC分类号： H01L39/02 ,  G06N10/00 ,  H01L39/22

摘要： Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δeff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).

公开(公告)号：US20220253740A1

公开(公告)日：2022-08-11

申请号：US17617388

申请日：2020-07-10

申请人： D-WAVE SYSTEMS INC.

发明人： Mark W. Johnson ,  Mauricio Reis Filho ,  Mark H. Volkmann ,  Ilya V. Perminov ,  Paul I. Bunyk

IPC分类号： G06N10/20

摘要： A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.

公开(公告)号：US11127893B2

公开(公告)日：2021-09-21

申请号：US16098801

申请日：2017-05-03

申请人： D-WAVE SYSTEMS INC.

发明人： Mark W. Johnson ,  Paul I. Bunyk ,  Andrew J. Berkley ,  Richard G. Harris ,  Kelly T. R. Boothby ,  Loren J. Swenson ,  Emile M. Hoskinson ,  Christopher B. Rich ,  Jan E. S. Johansson

IPC分类号： G06N10/00 ,  H01L39/22 ,  H01L39/02

摘要： Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

公开(公告)号：US11100418B2

公开(公告)日：2021-08-24

申请号：US16275816

申请日：2019-02-14

申请人： D-WAVE SYSTEMS INC.

发明人： Paul I. Bunyk ,  James King ,  Murray C. Thom ,  Mohammad H. Amin ,  Anatoly Yu Smirnov ,  Sheir Yarkoni ,  Trevor M. Lanting ,  Andrew D. King ,  Kelly T. R. Boothby

IPC分类号： G06N10/00 ,  G06F11/07

摘要： The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.

公开(公告)号：US20190220771A1

公开(公告)日：2019-07-18

申请号：US16307382

申请日：2017-06-07

申请人： D-WAVE SYSTEMS INC.

发明人： Kelly T. R. Boothby ,  Paul I. Bunyk

IPC分类号： G06N10/00 ,  G06F15/80

CPC分类号： G06N10/00 ,  B82Y10/00 ,  G06F15/80

摘要： Topologies for analog computing systems may include cells of qubits which may implement a tripartite graph and cross substantially orthogonally. Qubits may have an H-shape or an l-shape, qubits may change direction within a cell. Topologies may be comprised of two or more different sub-topologies. Qubits may be communicatively coupled to non-adjacent cells by long-range couplers. Long-range couplers may change direction within a cell. A cell may have two or more different type of long-range couplers. A cell may have shifted qubits, more than one type of inter-cell couplers, more than one type of intra-cell couplers and long-range couplers.

公开(公告)号：US20190087385A1

公开(公告)日：2019-03-21

申请号：US16173846

申请日：2018-10-29

申请人： D-WAVE SYSTEMS INC.

发明人： Alexander Maassen van den Brink ,  Peter Love ,  Mohammad H.S. Amin ,  Geordie Rose ,  David Grant ,  Miles F. H. Steininger ,  Paul I. Bunyk ,  Andrew J. Berkley

IPC分类号： G06F15/80 ,  H04L29/08 ,  H03K3/38 ,  G06N99/00 ,  G06F15/76 ,  B82Y10/00

CPC分类号： G06F15/80 ,  B82Y10/00 ,  G06F15/76 ,  G06N10/00 ,  H03K3/38 ,  H04L67/12

摘要： Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

公开(公告)号：US20170300817A1

公开(公告)日：2017-10-19

申请号：US15487295

申请日：2017-04-13

申请人： D-Wave Systems Inc.

发明人： Andrew D. King ,  Robert B. Israel ,  Paul I. Bunyk ,  Tomas J. Boothby ,  Steven P. Reinhardt ,  Aidan P. Roy ,  James A. King ,  Trevor M. Lanting ,  Abraham J. Evert

IPC分类号： G06N5/02 ,  G06N99/00

CPC分类号： G06N10/00 ,  G06N3/126

摘要： Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.

公开(公告)号：US11957065B2

公开(公告)日：2024-04-09

申请号：US17321819

申请日：2021-05-17

申请人： D-WAVE SYSTEMS INC.

发明人： Shuiyuan Huang ,  Byong H. Oh ,  Douglas P. Stadtler ,  Edward G. Sterpka ,  Paul I. Bunyk ,  Jed D. Whittaker ,  Fabio Altomare ,  Richard G. Harris ,  Colin C. Enderud ,  Loren J. Swenson ,  Nicolas C. Ladizinsky ,  Jason J. Yao ,  Eric G. Ladizinsky

IPC分类号： H10N60/01 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N60/85 ,  H10N69/00

CPC分类号： H10N60/0156 ,  H01L21/76891 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53285 ,  H10N60/85 ,  H10N69/00

摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.