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公开(公告)号：US5130598A
公开(公告)日：1992-07-14
申请号：US629063
申请日：1990-12-14
CPC分类号： F02D41/2096 , H01L41/042 , H02N2/067
摘要： An apparatus is provided for controllably connecting and disconnecting a piezoelectric actuator to and from an energy source to effect the displacement of a piezoelectric actuator for a fuel injector. Precise control of the timing and duration of the piezoelectric actuator is necessary to ensure that a proper quantity of fuel is delivered to each cylinder of an internal combustion engine. A charging and discharging means monitors the voltage level of the piezoelectric actuator, and the charging and discharging current of the piezoelectric actuator. Further, a smoothing means aids in leveling the charging and discharging current to better approximate a constant current to control the piezoelectric actuator providing a precise quantity of fuel to be delivered.
摘要翻译： 提供了一种用于将压电致动器可控地连接和断开与能量源的装置，以实现用于燃料喷射器的压电致动器的位移。 精确控制压电致动器的时间和持续时间是必要的，以确保将适量的燃料输送到内燃机的每个气缸。 充电和放电装置监视压电致动器的电压电平以及压电致动器的充电和放电电流。 此外，平滑装置有助于调平充电和放电电流，以更好地近似恒定电流，以控制压电致动器，从而提供精确量的要输送的燃料。
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公开(公告)号：US5945873A
公开(公告)日：1999-08-31
申请号：US990504
申请日：1997-12-15
申请人： James A. Antone , William J. Love
发明人： James A. Antone , William J. Love
CPC分类号： G05F3/265
摘要： A current mirror circuit is provided including a first and second transistors of a first conductivity type, the first transistor having a base connected to a base of the second transistor forming a base junction. A third transistor which is of a second conductivity type is connected in series with the first transistor and a collector of the third transistor is connected to the base junction of the first and second transistors. A fourth transistor which is of the second conductivity type is connected in series with the second transistor and has a base connected to a base of the third transistor forming a base junction. A collector of the second transistor is connected to the base junction of the third and fourth transistors. A first resistor is connected between an emitter of the third transistor and ground and a second resistor is connected between an emitter of the fourth transistor and ground. The circuit provides current matching over the first and second resistors where such resistors have about the same resistance values.
摘要翻译： 提供电流镜电路，其包括第一和第二第一导电类型的晶体管，第一晶体管具有连接到形成基极结的第二晶体管的基极的基极。 具有第二导电类型的第三晶体管与第一晶体管串联连接，第三晶体管的集电极连接到第一和第二晶体管的基极结。 具有第二导电类型的第四晶体管与第二晶体管串联连接，并且具有连接到形成基极结的第三晶体管的基极的基极。 第二晶体管的集电极连接到第三和第四晶体管的基极结。 第一电阻器连接在第三晶体管的发射极和地之间，第二电阻连接在第四晶体管的发射极和地之间。 该电路在第一和第二电阻器上提供电流匹配，其中这些电阻具有大约相同的电阻值。
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公开(公告)号：US5434527A
公开(公告)日：1995-07-18
申请号：US140934
申请日：1993-10-25
申请人： James A. Antone
发明人： James A. Antone
IPC分类号： H03K17/0412 , H03K17/691 , H03K17/16
CPC分类号： H03K17/04123 , H03K17/691
摘要： A circuit includes a high voltage energy source, a power transistor having a drain connected to the energy source and a source connected to a load, and a first capacitor connected between the power transistor gate and source. Also included is a first P-channel transistor connected in parallel with the first capacitor, and a second capacitor connected between the first P-channel transistor gate and drain. A transformer delivers positive voltage to the first capacitor to bias the power transistor ON, and delivers negative voltage to the second capacitor to bias the first P-channel transistor ON, which causes the energy stored in the first capacitor to discharge; thereby biasing the power transistor OFF.
摘要翻译： 电路包括高电压能量源，功率晶体管，其具有连接到能量源的漏极和连接到负载的源极，以及连接在功率晶体管栅极和源极之间的第一电容器。 还包括与第一电容器并联连接的第一P沟道晶体管，以及连接在第一P沟道晶体管栅极和漏极之间的第二电容器。 变压器向第一电容器提供正电压以偏置功率晶体管导通，并且向第二电容器输出负电压以偏置第一P沟道晶体管导通，这导致存储在第一电容器中的能量放电; 从而使功率晶体管偏压。
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公开(公告)号：US06437616B1
公开(公告)日：2002-08-20
申请号：US09741317
申请日：2000-12-19
IPC分类号： H03L706
CPC分类号： H03L7/089 , H03L7/0814 , H03L7/0818 , H03L7/095 , H03L7/10 , H03L2207/14 , Y10S331/02
摘要： A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block. The delay lock loop circuit is capable of handling a wide range of clock frequencies and a step increase or decrease in the clock frequency.
摘要翻译： 公开了一种延迟锁定环路电路，其包括延迟块，其接收时钟信号并将时钟信号延迟所选择的量以产生延迟的时钟信号。 相位检测器接收时钟信号和延迟的时钟信号，比较两个信号的相位并产生相位比较信号。 锁定检测器接收时钟信号和延迟的时钟信号，比较两个信号的定时并产生电位锁定指示信号。 控制器接收相位比较信号和电位锁定指示信号，并向延迟块提供延迟控制信号，以响应于相位比较信号改变所选择的延迟量。 响应于潜在的锁定指示信号，控制器以选定的间隔中断对延迟块的时钟信号，并且响应于在延迟块的时钟信号中断之后的电位锁定指示信号，产生真实的锁定指示信号。 延迟锁定环电路能够处理宽范围的时钟频率和时钟频率的逐步增加或减少。
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公开(公告)号：US5757224A
公开(公告)日：1998-05-26
申请号：US638419
申请日：1996-04-26
申请人： James A. Antone , Brian W. Mann
发明人： James A. Antone , Brian W. Mann
CPC分类号： G05F3/265
摘要： The present invention is directed toward a circuit for receiving an input current and for producing an output voltage proportional to the input current. The circuit includes a first transistor which receives the input current, and a second transistor connected to the first transistor, wherein the first and second transistors comprise a current mirror topology. A third transistor is connected in series with the first transistor, and an operational amplifier has an output which is connected to the base of the third transistor. The third transistor has a collector coupled to a base junction of the current mirror. The operational amplifier has a positive input terminal coupled to a collector of the second transistor through a first resistor, and a negative input terminal coupled to an emitter of the third transistor through a second resistor, the first and second resistors having substantially similar impedance values.
摘要翻译： 本发明涉及一种用于接收输入电流并产生与输入电流成比例的输出电压的电路。 电路包括接收输入电流的第一晶体管和连接到第一晶体管的第二晶体管，其中第一和第二晶体管包括电流镜拓扑。 第三晶体管与第一晶体管串联连接，运算放大器具有连接到第三晶体管的基极的输出端。 第三晶体管具有耦合到电流镜的基极结的集电极。 运算放大器具有通过第一电阻器耦合到第二晶体管的集电极的正输入端子，以及通过第二电阻器耦合到第三晶体管的发射极的负输入端子，第一和第二电阻器具有基本相似的阻抗值。
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公开(公告)号：US5724932A
公开(公告)日：1998-03-10
申请号：US733888
申请日：1996-10-18
申请人： James A. Antone
发明人： James A. Antone
CPC分类号： F02P19/025 , F02P19/021
摘要： In one aspect of the present invention, an apparatus for controlling the temperature of a plurality of glow plugs of a multi-cylinder internal combustion engine is disclosed. A voltage sensor produces a signal relative to the magnitude of the sensed voltage across a glow plug. A microprocessor compares the magnitude of the sensed signal with a preselected magnitude indicative of a predetermined temperature glow plug and responsively produces a current command signal. An alternator receives the current command signal and responsively delivers alternating current to the glow plugs.
摘要翻译： 在本发明的一个方面，公开了一种用于控制多缸内燃机的多个电热塞的温度的装置。 电压传感器相对于电热塞上感测到的电压的大小产生信号。 微处理器将感测到的信号的幅度与指示预定温度预热塞的预选幅度进行比较，并且响应地产生电流指令信号。 交流发电机接收电流指令信号并且响应地将交流电输送到电热塞。
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