公开(公告)号：US06989604B1

公开(公告)日：2006-01-24

申请号：US10672103

申请日：2003-09-26

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

IPC分类号： H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

摘要： An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

摘要翻译： 一种在其上具有基板和半导体器件的集成电路。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

公开(公告)号：US06723635B1

公开(公告)日：2004-04-20

申请号：US10115245

申请日：2002-04-04

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Steven C. Avanzino ,  John E. Sanchez, Jr. ,  Suzette K. Pangrle

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.

摘要翻译： 通过在阻挡金属层沉积之前沉积具有富硅表面的薄的，保形的碳化硅衬垫，可以防止在大马士革加工过程中低k ILD降解。 实施例包括在多孔低k电介质层中形成双镶嵌开口，沉积具有衬在开口上的富硅表面的薄碳化硅衬垫，沉积阻挡金属层，例如Ta / TaN复合材料，并用 铜。

公开(公告)号：US06617176B1

公开(公告)日：2003-09-09

申请号：US10152861

申请日：2002-05-21

申请人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

发明人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

IPC分类号： H01L2166

CPC分类号： H01L22/24 ,  G01N1/32 ,  H01L22/34

摘要： A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

摘要翻译： 通过形成测试样品并测量从金属化层（40）穿过阻挡层（30）（例如耐火材料）的铜（Cu）渗透性来确定沉积的薄共形阻挡层（30）的有效性的方法（M） 金属，其氮化物，它们的碳化物或其它化合物）通过薄的绝缘介电层（20）（例如SiO 2）和半导体（10）衬底（例如Si）中，其中迁移金属 离子和半导体离子被检测/监测，并且其中检测/监测包括（1）剥离绝缘介电层（20）和阻挡层（30）的至少一部分和（2）检查半导体衬底（10） ）表面，从而提高互连可靠性，提高耐迁移性，提高耐腐蚀性，减少铜扩散，从而形成试样装置。

公开(公告)号：US06657304B1

公开(公告)日：2003-12-02

申请号：US10165510

申请日：2002-06-06

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

IPC分类号： H01L2352

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

摘要翻译： 一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。