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    Conformal barrier liner in an integrated circuit interconnect
    2.
    发明授权
    Conformal barrier liner in an integrated circuit interconnect 有权
    集成电路互连中的保形阻挡衬垫

    公开(公告)号：US06657304B1

    公开(公告)日：2003-12-02

    申请号：US10165510

    申请日：2002-06-06

    申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    IPC分类号： H01L2352

    CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

    摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

    摘要翻译： 一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

    Conformal barrier liner in an integrated circuit interconnect
    3.
    发明授权
    Conformal barrier liner in an integrated circuit interconnect 有权
    集成电路互连中的保形阻挡衬垫

    公开(公告)号：US06989604B1

    公开(公告)日：2006-01-24

    申请号：US10672103

    申请日：2003-09-26

    申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

    摘要： An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

    摘要翻译： 一种在其上具有基板和半导体器件的集成电路。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

    METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED
    5.
    发明授权
    METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED 失效
    用于通过形成测试样本设备来确定阻隔层有效性的方法，并且使用用于制造生产半导体器件的金属渗透测量技术和形成的测试样本设备

    公开(公告)号：US06617176B1

    公开(公告)日：2003-09-09

    申请号：US10152861

    申请日：2002-05-21

    申请人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

    发明人： John E. Sanchez, Jr. ,  Pin-Chin Connie Wang ,  Christy Mei-Chu Woo ,  Paul R. Besser

    IPC分类号： H01L2166

    CPC分类号： H01L22/24 ,  G01N1/32 ,  H01L22/34

    摘要： A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

    摘要翻译： 通过形成测试样品并测量从金属化层（40）穿过阻挡层（30）（例如耐火材料）的铜（Cu）渗透性来确定沉积的薄共形阻挡层（30）的有效性的方法（M） 金属，其氮化物，它们的碳化物或其它化合物）通过薄的绝缘介电层（20）（例如SiO 2）和半导体（10）衬底（例如Si）中，其中迁移金属 离子和半导体离子被检测/监测，并且其中检测/监测包括（1）剥离绝缘介电层（20）和阻挡层（30）的至少一部分和（2）检查半导体衬底（10） ）表面，从而提高互连可靠性，提高耐迁移性，提高耐腐蚀性，减少铜扩散，从而形成试样装置。

    Movable terminal in a two terminal memory array
    6.
    发明授权
    Movable terminal in a two terminal memory array 失效
    两个终端存储器阵列中的可移动终端

    公开(公告)号：US07701834B2

    公开(公告)日：2010-04-20

    申请号：US11037971

    申请日：2005-01-18

    申请人： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    发明人： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    IPC分类号： G11B9/00

    CPC分类号： G11B9/08 ,  B82Y10/00 ,  G11B9/1445

    摘要： A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

    摘要翻译： 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。