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    Conformal barrier liner in an integrated circuit interconnect
    1.
    发明授权
    Conformal barrier liner in an integrated circuit interconnect 有权
    集成电路互连中的保形阻挡衬垫

    公开(公告)号：US06657304B1

    公开(公告)日：2003-12-02

    申请号：US10165510

    申请日：2002-06-06

    申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    IPC分类号： H01L2352

    CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

    摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

    摘要翻译： 一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

    Conformal barrier liner in an integrated circuit interconnect
    3.
    发明授权
    Conformal barrier liner in an integrated circuit interconnect 有权
    集成电路互连中的保形阻挡衬垫

    公开(公告)号：US06989604B1

    公开(公告)日：2006-01-24

    申请号：US10672103

    申请日：2003-09-26

    申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

    摘要： An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

    摘要翻译： 一种在其上具有基板和半导体器件的集成电路。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

    Graded low-k middle-etch stop layer for dual-inlaid patterning
    5.
    发明授权
    Graded low-k middle-etch stop layer for dual-inlaid patterning 有权
    用于双镶嵌图案的分级低k中间蚀刻停止层

    公开(公告)号：US06525428B1

    公开(公告)日：2003-02-25

    申请号：US10183458

    申请日：2002-06-28

    申请人： Minh Van Ngo ,  Steven C. Avanzino ,  Christy Mei-Chu Woo ,  John E. Sanchez

    发明人： Minh Van Ngo ,  Steven C. Avanzino ,  Christy Mei-Chu Woo ,  John E. Sanchez

    IPC分类号： H01L2348

    CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

    摘要： Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.

    摘要翻译： 改进的蚀刻选择性，阻挡金属润湿和降低的互连电容通过实施使用包括第一碳化硅层，第一碳化硅上的富硅层和第二碳化硅层上的第二碳化硅层的分级中间蚀刻停止层的镶嵌加工来实现 富硅层。 实施例包括在下部封装的Cu线上顺序沉积多孔低k电介质层，沉积渐变的中间蚀刻停止层，在分级中间蚀刻停止层上沉积多孔低k电介质层，形成双镶嵌开口露出 在沟槽开口的底部的富硅表面，沉积种子层，沉积阻挡中间层，如Ta或Ta / TaN复合材料，并用Cu填充开口。

    Elimination of residual materials in a multiple-layer interconnect structure
    6.
    发明授权
    Elimination of residual materials in a multiple-layer interconnect structure 失效
    消除多层互连结构中的残留材料

    公开(公告)号：US6153933A

    公开(公告)日：2000-11-28

    申请号：US925821

    申请日：1997-09-05

    申请人： Darin A. Chan ,  Steven C. Avanzino ,  Subramanian Venkatkrishnan ,  Minh Van Ngo ,  Christy Mei-Chu Woo de la Girond'arc ,  Diana M. Schonauer

    发明人： Darin A. Chan ,  Steven C. Avanzino ,  Subramanian Venkatkrishnan ,  Minh Van Ngo ,  Christy Mei-Chu Woo de la Girond'arc ,  Diana M. Schonauer

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L21/76819 ,  H01L23/5329 ,  H01L2924/0002

    摘要： A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer interconnect. The second layer interconnect also includes a second layer dielectric through which at least one second layer conductor extends. However, the second layer interconnect is created by first forming a thick second later dielectric layer and then reducing the thickness of the second layer dielectric prior to a patterning step. As a result topographical irregularities that may have carried over to the second layer interconnect from the first layer interconnect are removed by providing a substantially planar surface on the second layer dielectric.

    摘要翻译： 使用镶嵌技术形成集成电路中的多层互连结构。 第一层互连具有第一介电层，至少一个第一层导体通过第一介电层延伸。 然后在第一层互连上形成第二层互连。 第二层互连还包括第二层电介质，至少一层第二层导体延伸穿过第二层电介质。 然而，第二层互连通过首先形成厚的第二次介质层，然后在图案化步骤之前减小第二层电介质的厚度而产生。 因此，可以通过在第二层电介质上提供基本平坦的表面来去除可能已经承载到来自第一层互连的第二层互连的拓扑不规则。

    Composite tantalum nitride/tantalum copper capping layer
    7.
    发明授权
    Composite tantalum nitride/tantalum copper capping layer 有权
    复合氮化钽/钽铜覆盖层

    公开(公告)号：US07157795B1

    公开(公告)日：2007-01-02

    申请号：US10934511

    申请日：2004-09-07

    申请人： Darrell M. Erb ,  Steven C. Avanzino ,  Christy Mei-Chu Woo

    发明人： Darrell M. Erb ,  Steven C. Avanzino ,  Christy Mei-Chu Woo

    IPC分类号： H01L23/48

    CPC分类号： H01L21/2855 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  Y10S438/927

    摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.

    摘要翻译： 通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。 实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

    Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films
    9.
    发明授权
    Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films 失效
    化学机械抛光浆料配方及钨钛薄膜的制备方法

    公开(公告)号：US5916855A

    公开(公告)日：1999-06-29

    申请号：US829704

    申请日：1997-03-26

    申请人： Steven C. Avanzino ,  Christy Mei-Chu Woo ,  Diana Marie Schonauer ,  Peter Austin Burke

    发明人： Steven C. Avanzino ,  Christy Mei-Chu Woo ,  Diana Marie Schonauer ,  Peter Austin Burke

    IPC分类号： C09G1/02 ,  C09K3/14 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/306

    CPC分类号： C09G1/02 ,  C09K3/1463 ,  H01L21/3212

    摘要： A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.

    摘要翻译： 抛光浆料组合物及其通过晶片的化学机械抛光来制造硅半导体晶片的平面化的方法。 使用三价铁钨氧化剂，过硫酸铵钛氧化剂，脂肪酸悬浮剂，小直径和紧密直径范围的氧化铝颗粒，涂覆有溶解度涂层和化学稳定剂的浆料配方提供高钨和钛抛光 对二氧化硅具有高选择性的速率，以及用于钨局部互连应用的良好的氧化物缺陷率。 一种制备钨浆料的方法包括首先用具有悬浮剂的含水浓缩物中将紧密直径范围的小直径氧化铝颗粒充分混合，然后与水和氧化剂混合。 通过该方法制备的铁盐钨浆通过插塞和局部互连应用提供优异的钨酸盐抛光特性。