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    Method of forming low resistance barrier on low k interconnect
    3.
    发明授权
    Method of forming low resistance barrier on low k interconnect 有权
    在低k互连上形成低电阻势垒的方法

    公开(公告)号：US06555461B1

    公开(公告)日：2003-04-29

    申请号：US09884059

    申请日：2001-06-20

    申请人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Minh Van Ngo

    发明人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Minh Van Ngo

    IPC分类号： H01L214763

    CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.

    摘要翻译： 用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。 在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。 诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。 执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。 阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。 薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。

    Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
    4.
    发明授权
    Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer 失效
    在无电镀铜种子层的低k互连上形成低电阻势垒的方法

    公开(公告)号：US06509267B1

    公开(公告)日：2003-01-21

    申请号：US09884058

    申请日：2001-06-20

    申请人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Connie Pin-Chin Wang

    发明人： Christy Mei-Chu Woo ,  Suzette K. Pangrle ,  Connie Pin-Chin Wang

    IPC分类号： H01L2144

    CPC分类号： H01L21/76844 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76873

    摘要： A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate. The second metal layer serves as a nucleation step for electrolessly plating a copper seed layer.

    摘要翻译： 用于形成金属互连结构的方法在电介质层的图案化开口内提供诸如氮化物之类的阻挡材料的共形层。 在将开口蚀刻到电介质层上之后，阻挡材料沉积，停止在扩散阻挡层上。 诸如钽的金属阻挡材料的第一层被共形沉积在阻挡材料上。 执行定向蚀刻，其去除水平氮化物和钽，留下图案化开口的侧壁上的氮化物和钽。 阻挡材料在覆盖导电材料的扩散阻挡层的蚀刻期间以及在随后的溅射蚀刻清洁期间防止介电层从导电材料（例如铜）中的污染。 薄的第二金属层被共形沉积，并且在开口的侧壁上形成合适的阻挡层，同时在第二金属层和下面的基底之间提供低的接触电阻。 第二金属层用作无机电镀铜籽晶层的成核步骤。

    Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material
    5.
    发明授权
    Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material 有权
    在沉积由腐蚀性材料构成的电介质之后形成封装层

    公开(公告)号：US06472336B1

    公开(公告)日：2002-10-29

    申请号：US09511585

    申请日：2000-02-23

    申请人： Suzette K. Pangrle ,  Minh Van Ngo ,  Richard J. Huang

    发明人： Suzette K. Pangrle ,  Minh Van Ngo ,  Richard J. Huang

    IPC分类号： H01L2131

    CPC分类号： H01L21/76801 ,  C23C16/401 ,  H01L21/31629 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer. An encapsulating layer is formed over the corrosive dielectric material on the first semiconductor wafer and on the reaction chamber to prevent contact of the corrosive dielectric material to any exposed structure of a second semiconductor wafer to be subsequently placed into the reaction chamber when such an exposed structure is reactive with the corrosive dielectric material.

    摘要翻译： 绝缘材料形成为围绕集成电路的互连结构。 将第一半导体晶片放置在用于形成围绕第一半导体晶片上的集成电路的互连结构的绝缘材料的反应室中。 沉积具有低介电常数的腐蚀介电材料以包围互连结构，并且腐蚀介电材料填充互连结构之间的任何间隙。 在反应室内进行腐蚀性电介质材料的沉积，并且在第一半导体晶片上沉积腐蚀性电介质材料期间，腐蚀性电介质材料沉积在反应室上。 在第一半导体晶片上和反应室上的腐蚀介质材料上形成封装层，以防止腐蚀性电介质材料与任何暴露的第二半导体晶片的结构接触，随后将其放置在反应室中， 与腐蚀性介电材料反应。

    Method for removing anti-reflective coating layer using plasma etch process before contact CMP
    6.
    发明授权
    Method for removing anti-reflective coating layer using plasma etch process before contact CMP 有权
    在接触CMP之前使用等离子体蚀刻工艺去除抗反射涂层的方法

    公开(公告)号：US06291296B1

    公开(公告)日：2001-09-18

    申请号：US09416382

    申请日：1999-10-12

    申请人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

    发明人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/951

    摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.

    摘要翻译： 本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。 在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层 堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。 此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

    Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
    7.
    发明授权
    Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines 失效
    降低半导体互连线中应力诱发空隙的发生率的方法

    公开(公告)号：US06171947B2

    公开(公告)日：2001-01-09

    申请号：US09209367

    申请日：1998-12-08

    申请人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo ,  Stephan Keetai Park ,  Susan Tovar

    发明人： Suzette K. Pangrle ,  Paul R. Besser ,  Minh Van Ngo ,  Stephan Keetai Park ,  Susan Tovar

    IPC分类号： H01L2131

    CPC分类号： H01L21/3145 ,  H01L21/76834

    摘要： In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing. The pre-ILD annealing results in a substantially reduced incidence of stress-induced voiding in the underlying interconnect lines. Furthermore, the pre-ILD annealing can be combined with other advantageous process environments to more significantly reduce the incidence of stress-induced voiding in the underlying interconnect lines. Such combinations include process temperature reduction to below about 380 degrees Celsius and reduction of silane flow rate to less than about sixty standard cubic centimeters per minute.

    摘要翻译： 在用于在衬底的微电路互连线上形成层间电介质（ILD）涂层的方法中，衬底和互连线在沉积ILD之前被退火。 通过使用等离子体增强化学气相沉积形成后退火SiON层。 使用由氮气，一氧化二氮和硅烷气体形成的等离子体的沉积，其中气体以稳定的流速分配并由射频电源激励。 等离子体反应形成沉积在半导体衬底上的SiON。 此外，在沉积期间，对沉积温度和工艺压力进行微调，以控制SiON层的光学特性。 测试SiON层的可接受的光学性能，并且用SiO 2层涂覆可接受的SiON层以完成ILD的形成。 一旦形成了ILD，底物就可以进行进一步的处理。 前ILD退火导致底层互连线中应力诱发的排泄的发生率显着降低。 此外，前ILD退火可以与其他有利的工艺环境组合，以更显着地降低底层互连线中的应力诱发的排空的发生。 这样的组合包括将工艺温度降低至低于约380摄氏度，并将硅烷流速降低至小于约60标准立方厘米每分钟。

    Coherent alloy diffusion barrier for integrated circuit interconnects
    9.
    发明授权
    Coherent alloy diffusion barrier for integrated circuit interconnects 有权
    用于集成电路互连的相干合金扩散屏障

    公开(公告)号：US06462417B1

    公开(公告)日：2002-10-08

    申请号：US09772750

    申请日：2001-01-29

    申请人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Minh Van Ngo ,  Suzette K. Pangrle

    发明人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Minh Van Ngo ,  Suzette K. Pangrle

    IPC分类号： H01L2348

    CPC分类号： H01L21/76844 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53209 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an alloy-barrier layer lining the channel opening, and a conductor core filling the channel opening. An alloy layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form an alloy-barrier to diffusion of the material of the conductor core to the channel dielectric layer. The alloy-barrier layer is reacted with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.

    摘要翻译： 提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有通道开口，衬在沟道开口的合金阻挡层和填充沟道开口的导体芯。 沉积合金层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成对导体芯的材料扩散到沟道介电层的合金阻挡层。 合金阻挡层与导体芯和沟道电介质层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯在双重嵌入式集成电路中的芯体扩散。