公开(公告)号：US20100169623A1

公开(公告)日：2010-07-01

申请号：US12345162

申请日：2008-12-29

Applicant: David Dice

Inventor： David Dice

IPC: G06F9/318

CPC classification number: G06F9/3842 ,  G06F9/526 ,  G06F9/528

Abstract: Hardware-based transactional memory mechanisms, such as Speculative Lock Elision (SLE), may allow multiple threads to concurrently execute critical sections protected by the same lock as speculative transactions. Such transactions may abort due to contention or due to misidentification of code as a critical section. In various embodiments, speculative execution mechanisms may be augmented with software and/or hardware contention management mechanisms to reduce abort rates. Speculative execution hardware may send a hardware interrupt signal to notify software components of a speculative execution event (e.g., abort). Software components may respond by implementing concurrency-throttling mechanisms and/or by determining a mode of execution (e.g., speculative, non-speculative) for a given section and communicating that determination to the hardware speculative execution mechanisms, e.g., by writing it into a lock predictor cache. Subsequently, hardware speculative execution mechanisms may determine a preferred mode of execution for the section by reading the corresponding entry from the lock predictor cache.

Abstract translation: 基于硬件的事务性存储机制（如推测锁定Elision（SLE））可能允许多个线程同时执行由与投机事务相同锁定的关键部分。 此类交易可能由于争用或由于将代码误认为关键部分而中止。 在各种实施例中，可以用软件和/或硬件争用管理机制来增强推测执行机制，以减少中止率。 推测执行硬件可以发送硬件中断信号以通知软件组件推测执行事件（例如，中止）。 软件组件可以通过实现并发调节机制和/或通过确定给定部分的执行模式（例如，推测性，非推测性）来进行响应，并将该确定传达给硬件推测执行机制，例如通过将其写入 锁定预测器缓存。 随后，硬件推测执行机制可以通过从锁定预测器高速缓存读取相应的条目来确定该部分的优选执行模式。

公开(公告)号：US07640402B2

公开(公告)日：2009-12-29

申请号：US11699802

申请日：2007-01-30

Applicant: David Dice ,  Nir N. Shavit ,  Ori Shalev ,  Mark Moir

Inventor： David Dice ,  Nir N. Shavit ,  Ori Shalev ,  Mark Moir

IPC: G06F13/00

Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel and use the same shared data without causing corruption to the shared data. For example, during a commit phase, a corresponding transaction can attempt to increment a globally accessible version information variable and store a current value of the globally accessible version information variable for updating version information associated with modified data regardless of whether an associated attempt by the corresponding transaction to modify the globally accessible version information variable was successful. As an alternative mode, a corresponding transaction can merely read and store a current value of the globally accessible version information variable without attempting to update the globally accessible version information variable before such use. In yet another application, a parallel processing environment implements a combination of both aforementioned modes depending on a self-abort rate of the transaction.

公开(公告)号：US20090282386A1

公开(公告)日：2009-11-12

申请号：US12250409

申请日：2008-10-13

Applicant: Mark S. Moir ,  David Dice

Inventor： Mark S. Moir ,  David Dice

IPC: G06F9/44

CPC classification number: G06F9/466

Abstract: Systems and methods for managing divergence of best effort transactional support mechanisms in various transactional memory implementations using a portable transaction interface are described. This interface may be implemented by various combinations of best effort hardware features, including none at all. Because the features offered by this interface may be best effort, a default (e.g., software) implementation may always be possible without the need for special hardware support. Software may be written to the interface, and may be executable on a variety of platforms, taking advantage of best effort hardware features included on each one, while not depending on any particular mechanism. Multiple implementations of each operation defined by the interface may be included in one or more portable transaction interface libraries. Systems and/or application software may be written as platform-independent and/or portable, and may call functions of these libraries to implement the operations for a targeted execution environment.

Abstract translation: 描述了使用便携式事务接口来管理各种事务存储器实现中的尽力而为事务支持机制的分歧的系统和方法。 该接口可以通过尽力而为的硬件特征的各种组合来实现，包括根本没有。 由于此接口提供的功能可能是最大的努力，默认（例如，软件）实现可能始终是可能的，而不需要特殊的硬件支持。 可以将软件写入接口，并且可以在各种平台上执行，利用包括在每个平台上的尽力而为的硬件特征，而不依赖于任何特定的机制。 由接口定义的每个操作的多个实现可以包括在一个或多个便携式事务接口库中。 系统和/或应用软件可以被写为独立于平台的和/或可移植的，并且可以调用这些库的功能来实现针对性的执行环境的操作。

公开(公告)号：US07200846B2

公开(公告)日：2007-04-03

申请号：US10212509

申请日：2002-08-05

Applicant: David Dice ,  Paula J. Bishop

Inventor： David Dice ,  Paula J. Bishop

IPC: G06F9/00

CPC classification number: G06F9/485 ,  G06F9/526 ,  G06F2209/481

Abstract: When a thread of program execution on a computer system is executing a critical code section, i.e., a code section whose preemption could result in inconsistency, it asserts an indicator of that fact. When the system's scheduler reschedules the thread for execution, it determines whether the indicator is asserted. If the indicator is asserted, the scheduler does not cause the thread immediately to resume execution where the thread left off when it was preempted. Instead, the scheduler has the thread's signal handler execute in such a manner that the thread performs inconsistency-avoiding operations.

Abstract translation: 当计算机系统上的程序执行线程正在执行关键代码部分，即其抢占可能导致不一致的代码部分时，它断言该事实的指示符。 当系统的调度器重新排列线程以执行时，它确定指示符是否被断言。 如果指示器被断言，则调度程序不会在线程被抢占时线程立即恢复执行。 相反，调度器以线程执行不一致避免操作的方式执行线程的信号处理程序。

公开(公告)号：US07024633B1

公开(公告)日：2006-04-04

申请号：US09855968

申请日：2001-05-15

Applicant: Ronald J. Mann ,  David Dice ,  David B. Therkelsen

Inventor： Ronald J. Mann ,  David Dice ,  David B. Therkelsen

IPC: G06F3/00 ,  G06F9/00 ,  G06F17/00

CPC classification number: G06F8/34

Abstract: Mechanisms and techniques provide a system for composing a complex constructs for use on a graphical display of a computerized device. The system receives a selection of basic constructor objects for use in the complex object. The basic constructor objects are chosen from a set of basic constructor object types including a button object type, a dial object type, an edit object type, and a container object type. The systems also receives a selection of one or more personalities to assign to the basic constructor objects. The personalities define extensions to basic constructor object operation and define a view for the object when rendered on an interface. The system combines the personalities and the basic constructor objects to define complex constructs such as menus, a scrollbars and the like. Personalities can be modified to alter the complex construct from one operational state to another.

Abstract translation: 机制和技术提供了一种用于组合复杂构造以在计算机化设备的图形显示上使用的系统。 系统接收用于复杂对象的基本构造函数对象的选择。 基本构造函数对象从一组基本构造函数对象类型中选择，包括按钮对象类型，拨号对象类型，编辑对象类型和容器对象类型。 系统还接收一个或多个个性的选择以分配给基本构造函数对象。 个性定义对基本构造函数对象操作的扩展，并在对接口进行呈现时定义对象的视图。 该系统结合了个性和基本构造函数对象来定义复杂的构造，如菜单，滚动条等。 可以修改个性以将复杂构造从一个操作状态改变为另一个。

公开(公告)号：US07016923B2

公开(公告)日：2006-03-21

申请号：US10287851

申请日：2002-11-05

Applicant: Alexander T. Garthwaite ,  Christine H. Flood ,  David Dice

Inventor： Alexander T. Garthwaite ,  Christine H. Flood ,  David Dice

IPC: G06F12/00

CPC classification number: G06F12/0276 ,  Y10S707/99953 ,  Y10S707/99957

Abstract: A computer system employing a plurality of concurrent threads to perform tasks that dynamically identify further similar tasks employs a double-ended queue (“deque”) to list the dynamically identified tasks. If a thread's deque runs out of tasks while other threads' deques have tasks remaining, the thread whose deque has become empty will remove one or more entries from another thread's deque and perform the tasks thereby identified. When a thread's deque becomes too full, it may allocate space for another deque, transfer entries from its existing deque, place an identifier of the existing deque into the new deque, and adopt the new deque as the one that it uses for storing and retrieving task identifiers. Alternatively, it may transfer some of the existing deque's entries into a newly allocated array and place an identifier of that array into the existing deque. The thread thereby deals with deque overflows without introducing additional synchronization requirements or restricting the deque's range of use.

Abstract translation: 采用多个并行线程来执行动态地识别进一步类似任务的任务的计算机系统采用双端队列（“deque”）列出动态识别的任务。 如果一个线程的deque用完了任务，而其他线程的deques有剩余的任务，则其deque已经变空的线程将从另一个线程的deque中删除一个或多个条目，然后执行这样识别的任务。 当一个线程的deque变得太满时，它可以为另一个deque分配空间，从现有deque传输条目，将现有deque的标识符放置到新deque中，并采用新的deque作为它用于存储和检索的deque 任务标识符。 或者，它可以将一些现有deque的条目转移到新分配的数组中，并将该数组的标识符放置到现有deque中。 因此，线程处理德克尔溢出，而不引入额外的同步要求或限制德克的使用范围。

公开(公告)号：US06862674B2

公开(公告)日：2005-03-01

申请号：US10163677

申请日：2002-06-06

Applicant: David Dice ,  Alexander T. Garthwaite

Inventor： David Dice ,  Alexander T. Garthwaite

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0269 ,  G06F12/0261 ,  Y10S707/99953 ,  Y10S707/99956

Abstract: Mechanisms and techniques operate in a computerized device to perform a memory management technique such as garbage collection. The mechanisms and techniques operate to detect, within a storage structure associated with a thread, general memory references that reference storage locations in a general memory area such as a heap. The storage structure may be a stack utilized by the thread, which may be, for example, a Java thread, during operation of the thread in the computerized device. The system maintains a reference structure containing an association to the general memory area for each detected general memory reference within the storage structure. The system then operates a memory management technique on the general memory area for locations in the general memory area other than those for which an association to the general memory area is maintained in the reference structure, thus increasing the performance of the memory management technique.

Abstract translation: 机制和技术在计算机化设备中运行，以执行诸如垃圾收集之类的存储器管理技术。 机制和技术操作以在与线程相关联的存储结构内检测引用诸如堆的通用存储器区域中的存储位置的一般存储器引用。 存储结构可以是在计算机化设备中的线程的操作期间由线程使用的栈，其可以是例如Java线程。 系统维护包含与存储结构内的每个检测到的通用存储器引用的一般存储器区域的关联的参考结构。 然后，系统在通用存储器区域中对存储器管理技术中的存储器管理技术进行操作，该存储器管理技术在通用存储器区域中的位置之外，而与在一般存储器区域的关联保持在参考结构中的位置不同，从而增加了存储器管理技术的

公开(公告)号：US06308315B1

公开(公告)日：2001-10-23

申请号：US09172153

申请日：1998-10-14

Applicant: David Dice ,  Andrew F. Herrick ,  Ronald J. Mann

Inventor： David Dice ,  Andrew F. Herrick ,  Ronald J. Mann

IPC: G06F945

CPC classification number: G06F8/433 ,  G06F8/443 ,  G06F9/4488

Abstract: A code generating system generates, from code in a program, native code that is executable by a computer system. The computer system includes a memory subsystem including a heap in which objects are stored and a stack in which method variables are stored. The code generating system may be included in a just-in-time compiler used to generate native code that is executable by a computer system, from a program in Java Byte Code form, and specifically determines, in response to Java Byte Code representative of an operator for enabling instantiation of a new object, whether the object to be instantiated contains a variable to be used in processing of the received program code portion which can be promoted to a method variable, and, if so, generates native code to enable said variable to be instantiated on the stack.

Abstract translation: 代码生成系统从程序中的代码生成可由计算机系统执行的本地代码。 计算机系统包括存储子系统，该存储器子系统包括存储对象的堆以及存储方法变量的堆栈。 代码生成系统可以被包括在用于生成可由计算机系统执行的本地代码的即时编译器中，从Java字节代码形式的程序中，并且具体地确定响应于代表代码的Java字节代码 运算符用于启用新对象的实例化，是否要被实例化的对象包含要被用于处理接收到的程序代码部分的变量，可以被提升为方法变量，并且如果是，则生成本地代码以使得所述变量 要在堆栈上实例化。

公开(公告)号：US5778211A

公开(公告)日：1998-07-07

申请号：US602158

申请日：1996-02-15

Applicant: Paul H. Hohensee ,  David Dice

Inventor： Paul H. Hohensee ,  David Dice

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F9/00 ,  G06F9/46

CPC classification number: G06F9/3865 ,  G06F9/45554

Abstract: A digital computer system comprises a precise exception handling processor and a control subsystem. The precise exception handling processor performs processing operations under control of instructions. The precise exception handling processor is constructed in accordance with a precise exception handling model, in which, if an exception condition is detected in connection with an instruction, the exception condition is processed in connection with the instruction. The precise exception handling processor further includes a pending exception indicator having a pending exception indication state and a no pending exception indication state. The control subsystem provides a series of instructions to the precise exception handling processor to facilitate emulation of at least one emulated program instruction. The emulated program instruction is constructed to be processed by a delayed exception handling processor which is constructed in accordance with a delayed exception handling model, in which if an exception is detected during processing of an instruction, the exception condition is processed in connection with a subsequent instruction. The series of instructions provided by the control subsystem in emulation of the emulated program instruction controls the precise exception handling processor to (i) determine whether the pending exception indicator is in the pending exception indication state and, if so, to invoke a routine to process the pending exception and condition the pending exception indicator to the no pending exception indication state (ii) perform processing operations in accordance with the emulated processing instruction; and (iii) if an exception condition is detected during the processing operations, to invoke an exception handler in accordance with the processor's precise exception handling model to condition the pending exception indicator to the pending exception indication state, so that the exception condition will be processed during processing operations for a subsequent emulated program instruction.

公开(公告)号：US5765206A

公开(公告)日：1998-06-09

申请号：US608571

申请日：1996-02-28

Applicant: Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

Inventor： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

IPC: G06F9/455 ,  G06F9/318 ,  G06F9/34 ,  G06F12/10

CPC classification number: G06F9/45537 ,  G06F12/1036 ,  G06F12/109 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/34

Abstract: A processor processes a segmented to linear virtual address conversion instruction to convert segmented virtual addresses in a segmented virtual address space to a linear virtual address in a linear virtual address space. The segmented virtual address space comprises a plurality of segments each identified by a segment identifier, each segment comprising at least one page identified by a page identifier. The linear virtual address space includes a plurality of pages each identified by a page identifier. In processing the segmented to linear virtual address conversion instruction, the processor uses a plurality of segmented to linear virtual address conversion descriptors, each associated with a page in the segmented virtual address space, each segmented to linear virtual address conversion descriptor identifying the page identifier of one of the pages in the linear virtual address space. The segmented to linear virtual address conversion instruction includes a segmented virtual address identifier in the segmented virtual address space. In processing the segmented to linear virtual address conversion instruction, the processor uses the segmented virtual address identifier in the segmented to linear virtual address conversion instruction to select one of the segmented to linear virtual address conversion descriptors. After selecting a segmented to linear virtual address conversion descriptor, the processor uses the page identifier of the linear virtual address space from the selected segmented to linear virtual address conversion descriptor and the segmented virtual address identifier in the segmented to linear virtual address conversion instruction in generating a virtual address in the linear virtual address space.

Abstract translation: 处理器处理分段到线性虚拟地址转换指令，以将分段虚拟地址空间中的分段虚拟地址转换为线性虚拟地址空间中的线性虚拟地址。 分割的虚拟地址空间包括多个片段，每个片段由片段标识符标识，每个片段包括由页面标识符标识的至少一个页面。 线性虚拟地址空间包括由页面标识符标识的多个页面。 在处理分段到线性虚拟地址转换指令时，处理器使用多个分段到线性的虚拟地址转换描述符，每个分割到线性虚拟地址转换描述符与分段的虚拟地址空间中的一个页面相关联，每个划分为线性虚拟地址转换描述符， 线性虚拟地址空间中的一个页面。 分段到线性虚拟地址转换指令包括分段虚拟地址空间中的分段虚拟地址标识符。 在处理分段到线性虚拟地址转换指令时，处理器使用分段到线性虚拟地址转换指令中的分段虚拟地址标识符来选择分段到线性虚拟地址转换描述符之一。 在选择分段到线性虚拟地址转换描述符之后，处理器使用从所选择的分段到线性虚拟地址转换描述符的线性虚拟地址空间的页面标识符和分段到线性虚拟地址转换指令中的分段虚拟地址标识符，以生成 线性虚拟地址空间中的虚拟地址。