公开(公告)号：US5778211A

公开(公告)日：1998-07-07

申请号：US602158

申请日：1996-02-15

申请人： Paul H. Hohensee ,  David Dice

发明人： Paul H. Hohensee ,  David Dice

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F9/00 ,  G06F9/46

CPC分类号： G06F9/3865 ,  G06F9/45554

摘要： A digital computer system comprises a precise exception handling processor and a control subsystem. The precise exception handling processor performs processing operations under control of instructions. The precise exception handling processor is constructed in accordance with a precise exception handling model, in which, if an exception condition is detected in connection with an instruction, the exception condition is processed in connection with the instruction. The precise exception handling processor further includes a pending exception indicator having a pending exception indication state and a no pending exception indication state. The control subsystem provides a series of instructions to the precise exception handling processor to facilitate emulation of at least one emulated program instruction. The emulated program instruction is constructed to be processed by a delayed exception handling processor which is constructed in accordance with a delayed exception handling model, in which if an exception is detected during processing of an instruction, the exception condition is processed in connection with a subsequent instruction. The series of instructions provided by the control subsystem in emulation of the emulated program instruction controls the precise exception handling processor to (i) determine whether the pending exception indicator is in the pending exception indication state and, if so, to invoke a routine to process the pending exception and condition the pending exception indicator to the no pending exception indication state (ii) perform processing operations in accordance with the emulated processing instruction; and (iii) if an exception condition is detected during the processing operations, to invoke an exception handler in accordance with the processor's precise exception handling model to condition the pending exception indicator to the pending exception indication state, so that the exception condition will be processed during processing operations for a subsequent emulated program instruction.

公开(公告)号：US5765206A

公开(公告)日：1998-06-09

申请号：US608571

申请日：1996-02-28

申请人： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

发明人： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/318 ,  G06F9/34 ,  G06F12/10

CPC分类号： G06F9/45537 ,  G06F12/1036 ,  G06F12/109 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/34

摘要： A processor processes a segmented to linear virtual address conversion instruction to convert segmented virtual addresses in a segmented virtual address space to a linear virtual address in a linear virtual address space. The segmented virtual address space comprises a plurality of segments each identified by a segment identifier, each segment comprising at least one page identified by a page identifier. The linear virtual address space includes a plurality of pages each identified by a page identifier. In processing the segmented to linear virtual address conversion instruction, the processor uses a plurality of segmented to linear virtual address conversion descriptors, each associated with a page in the segmented virtual address space, each segmented to linear virtual address conversion descriptor identifying the page identifier of one of the pages in the linear virtual address space. The segmented to linear virtual address conversion instruction includes a segmented virtual address identifier in the segmented virtual address space. In processing the segmented to linear virtual address conversion instruction, the processor uses the segmented virtual address identifier in the segmented to linear virtual address conversion instruction to select one of the segmented to linear virtual address conversion descriptors. After selecting a segmented to linear virtual address conversion descriptor, the processor uses the page identifier of the linear virtual address space from the selected segmented to linear virtual address conversion descriptor and the segmented virtual address identifier in the segmented to linear virtual address conversion instruction in generating a virtual address in the linear virtual address space.

摘要翻译： 处理器处理分段到线性虚拟地址转换指令，以将分段虚拟地址空间中的分段虚拟地址转换为线性虚拟地址空间中的线性虚拟地址。 分割的虚拟地址空间包括多个片段，每个片段由片段标识符标识，每个片段包括由页面标识符标识的至少一个页面。 线性虚拟地址空间包括由页面标识符标识的多个页面。 在处理分段到线性虚拟地址转换指令时，处理器使用多个分段到线性的虚拟地址转换描述符，每个分割到线性虚拟地址转换描述符与分段的虚拟地址空间中的一个页面相关联，每个划分为线性虚拟地址转换描述符， 线性虚拟地址空间中的一个页面。 分段到线性虚拟地址转换指令包括分段虚拟地址空间中的分段虚拟地址标识符。 在处理分段到线性虚拟地址转换指令时，处理器使用分段到线性虚拟地址转换指令中的分段虚拟地址标识符来选择分段到线性虚拟地址转换描述符之一。 在选择分段到线性虚拟地址转换描述符之后，处理器使用从所选择的分段到线性虚拟地址转换描述符的线性虚拟地址空间的页面标识符和分段到线性虚拟地址转换指令中的分段虚拟地址标识符，以生成 线性虚拟地址空间中的虚拟地址。

公开(公告)号：US08683483B2

公开(公告)日：2014-03-25

申请号：US12054491

申请日：2008-03-25

申请人： Paul H. Hohensee

发明人： Paul H. Hohensee

IPC分类号： G06F9/46

CPC分类号： G06F9/5088 ,  G06F9/3851 ,  G06F2209/5022

摘要： Load-balancing threads among a plurality of processing units. The method may include a first processing unit executing a plurality of software threads using a respective plurality of hardware strands. The plurality of hardware strands may share at least one hardware resource within the first processing unit. The method may further include monitoring the at least one hardware resource, wherein, for each respective hardware strand. Monitoring may include, for each respective hardware resource of the at least one hardware resource: maintaining information regarding the respective hardware strand requesting to use the respective hardware resource but failing to do so because the respective hardware resource is in use, comparing the information to a threshold, and generating an interrupt if the information exceeds the threshold. One or more load-balancing operations may be performed in response to the interrupt.

摘要翻译： 在多个处理单元之间负载平衡线程。 该方法可以包括使用相应的多个硬件线执行多个软件线程的第一处理单元。 多个硬件链可以在第一处理单元内共享至少一个硬件资源。 该方法还可以包括监视至少一个硬件资源，其中，对于每个相应的硬件链。 对于至少一个硬件资源的每个相应的硬件资源，监视可以包括：维护关于相应的硬件链的信息，请求使用相应的硬件资源，但由于相应的硬件资源正在使用而不能这样做，将该信息与 阈值，如果信息超过阈值，则产生中断。 可以响应于中断来执行一个或多个负载平衡操作。

公开(公告)号：US08645651B2

公开(公告)日：2014-02-04

申请号：US12693815

申请日：2010-01-26

申请人： Antonios Printezis ,  Paul H. Hohensee

发明人： Antonios Printezis ,  Paul H. Hohensee

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0253 ,  G06F9/5022 ,  G06F12/0269

摘要： A method for queuing update buffers to enhance garbage collection. The method includes running an application thread and providing, for the application thread, a data structure including current and finished update buffer slots. The method includes providing an update buffer for the application thread and storing a pointer to the update buffer in the current update buffer slot. The method includes storing null in the finished update buffer slot and, with the application thread, writing to the update buffer. The thread may write a pointer to the filled update buffer in the finished update buffer slot after the buffer is filled. The method includes using a garbage collector thread to inspect the finished update buffer slot and claim filled buffers and change the pointer to null. The thread then obtains an empty update buffer and updates the current update buffer slot to point to the new buffer.

摘要翻译： 排队更新缓冲区以增强垃圾回收的方法。 该方法包括运行应用程序线程，并为应用程序线程提供包括当前和完成的更新缓冲区槽位的数据结构。 该方法包括为应用程序线程提供更新缓冲区，并在当前更新缓冲区槽中存储指向更新缓冲区的指针。 该方法包括在完成的更新缓冲区槽中存储空值，并与应用程序线程一起写入更新缓冲区。 在填充缓冲区之后，线程可能会在完成的更新缓冲区插槽中写入指向填充更新缓冲区的指针。 该方法包括使用垃圾回收器线程来检查已完成的更新缓冲区槽位并声明已填充的缓冲区，并将指针更改为null。 线程然后获得一个空的更新缓冲区，并更新当前的更新缓冲区槽位以指向新的缓冲区。

公开(公告)号：US07069421B1

公开(公告)日：2006-06-27

申请号：US09429094

申请日：1999-10-28

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Korbin S. Van Dyke ,  T. R. Ramesh

IPC分类号： G06F9/30

CPC分类号： G06F9/45533

摘要： A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.

摘要翻译： 微处理器芯片，以及用于该微处理器芯片的方法。 该芯片具有指令流水线电路和地址转换电路。 表查找电路索引到表中，该表具有与由地址转换电路翻译的每个相应地址范围相关联的条目。 该表的每个条目描述存在位于相应的相应地址范围内的指令的替代编码的可能性。 表查找电路检索对应于该地址的表条目，并可作为执行在计算机上执行的非主管模式程序的指令的基本指令周期的一部分。 中断电路与指令流水线电路协同设计，以至少部分地基于计算机的存储状态和指令的地址同步地触发执行过程指令的中断，指令的架构定义不是 要求中断。 用于中断的处理程序响应于表的内容，以影响指令流水线电路，以基于与该指令相关联的表条目的内容来实现对结构上可视数据操纵行为的控制或指令的控制传递行为。

公开(公告)号：US06826748B1

公开(公告)日：2004-11-30

申请号：US09339749

申请日：1999-06-24

申请人： Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

发明人： Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Niteen Aravind Patkar

IPC分类号： G06F944

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/45554 ,  G06F2009/45583

摘要： A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

摘要翻译： 用于执行该方法的方法和计算机。 在计算机上执行程序时，计算机使用通用寄存器文件的寄存器来存储指令结果。 描述可概要事件的简档信息可记录在通用寄存器文件中，因为可以描述事件的发生，而无需先将信息捕获到计算机的主存储器中。

公开(公告)号：US06763452B1

公开(公告)日：2004-07-13

申请号：US09339797

申请日：1999-06-24

申请人： Paul H. Hohensee ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  David L. Reese ,  Stephen C. Purcell

发明人： Paul H. Hohensee ,  John S. Yates, Jr. ,  Korbin S. Van Dyke ,  David L. Reese ,  Stephen C. Purcell

IPC分类号： G06F900

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/45554 ,  G06F2009/45583

摘要： A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events. A second CPU is configured to analyze the generated profile data, while the execution and profile data generation continue on the first CPU, and to control the execution of the program on the first CPU based at least in part on the analysis of the collected profile data.

摘要翻译： 一种用于执行该方法的方法和多处理器计算机。 第一个CPU有一个通用寄存器文件，一个通道管道和一个轮廓电路。 配置文件电路与指令管道可操作地互连，并在通用的硬件控制下。 配置文件电路和指令流水线协同互连，以检测在指令流水线中发生的可轮廓事件的发生。 配置文件电路可操作而无需软件干预，以便将描述可描述事件的简档信息记录到通用寄存器文件中，而无需首先将信息捕获到计算机的主存储器中。 录音本质上与可配置事件的发生同时发生。 第二CPU被配置为分析生成的简档数据，同时在第一CPU上继续执行和简档数据生成，并且至少部分地基于所收集的简档数据的分析来控制第一CPU上的程序的执行 。

公开(公告)号：US08782306B2

公开(公告)日：2014-07-15

申请号：US12699370

申请日：2010-02-03

申请人： Antonios Printezis ,  Paul H. Hohensee

发明人： Antonios Printezis ,  Paul H. Hohensee

IPC分类号： G06F13/00

CPC分类号： G06F12/0253 ,  G06F5/12 ,  G06F9/455 ,  G06F9/46 ,  G06F13/00

摘要： A method for queuing thread update buffers to enhance garbage collection. The method includes providing a global update buffer queue and a global array with slots for storing pointers to filled update buffers. The method includes with an application thread writing to the update buffer and, when filled, attempting to write the pointer for the update buffer to the global array. The array slot may be selected randomly or by use of a hash function. When the writing fails due to a non-null slot, the method includes operating the application thread to add the filled update buffer to the global update buffer queue. The method includes, with a garbage collector thread, inspecting the global array for non-null entries and, upon locating a pointer, claiming the filled update buffer. The method includes using the garbage collector thread to claim and process buffers added to the global update buffer queue.

摘要翻译： 排队线程更新缓冲区以增强垃圾回收的方法。 该方法包括提供全局更新缓冲器队列和全局阵列，其具有用于存储指向填充的更新缓冲器的指针的时隙。 该方法包括应用程序线程写入更新缓冲区，并在填充时尝试将更新缓冲区的指针写入全局数组。 可以随机地或通过使用散列函数来选择阵列时隙。 当由于非空插槽而导致写入失败时，该方法包括操作应用程序线程以将填充的更新缓冲区添加到全局更新缓冲区队列。 该方法包括：使用垃圾收集器线程，检查全局数组的非空条目，并在找到指针时声明填充的更新缓冲区。 该方法包括使用垃圾收集器线程来声明和处理添加到全局更新缓冲区队列中的缓冲区。

公开(公告)号：US20110185144A1

公开(公告)日：2011-07-28

申请号：US12693815

申请日：2010-01-26

申请人： Antonios Printezis ,  Paul H. Hohensee

发明人： Antonios Printezis ,  Paul H. Hohensee

IPC分类号： G06F12/02 ,  G06F9/455

CPC分类号： G06F12/0253 ,  G06F9/5022 ,  G06F12/0269

摘要： A method for queuing update buffers to enhance garbage collection. The method includes running an application thread and providing, for the application thread, a data structure including current and finished update buffer slots. The method includes providing an update buffer for the application thread and storing a pointer to the update buffer in the current update buffer slot. The method includes storing null in the finished update buffer slot and, with the application thread, writing to the update buffer. The thread may write a pointer to the filled update buffer in the finished update buffer slot after the buffer is filled. The method includes using a garbage collector thread to inspect the finished update buffer slot and claim filled buffers and change the pointer to null. The thread then obtains an empty update buffer and updates the current update buffer slot to point to the new buffer.

摘要翻译： 排队更新缓冲区以增强垃圾回收的方法。 该方法包括运行应用程序线程，并为应用程序线程提供包括当前和完成的更新缓冲区槽位的数据结构。 该方法包括为应用程序线程提供更新缓冲区，并在当前更新缓冲区槽中存储指向更新缓冲区的指针。 该方法包括在完成的更新缓冲区槽中存储空值，并与应用程序线程一起写入更新缓冲区。 在填充缓冲区之后，线程可能会在完成的更新缓冲区插槽中写入指向填充更新缓冲区的指针。 该方法包括使用垃圾回收器线程来检查已完成的更新缓冲区槽位并声明已填充的缓冲区，并将指针更改为null。 线程然后获得一个空的更新缓冲区，并更新当前的更新缓冲区槽位以指向新的缓冲区。

公开(公告)号：US20090204785A1

公开(公告)日：2009-08-13

申请号：US11982419

申请日：2007-10-31

申请人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/3802

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线识别来自第一页面的执行流程，其相关联的指示符元素指示第一架构。 或执行约定，到第二页，其相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。