公开(公告)号：US09898316B1

公开(公告)日：2018-02-20

申请号：US13200777

申请日：2011-09-30

申请人： Steve Chalmer ,  John Forecast ,  Matthew H. Fredette ,  Steven T. McClure ,  Serge J. Pirotte ,  David L. Reese

发明人： Steve Chalmer ,  John Forecast ,  Matthew H. Fredette ,  Steven T. McClure ,  Serge J. Pirotte ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F9/50

CPC分类号： G06F9/45545 ,  G06F9/45537 ,  G06F9/45558 ,  G06F9/5077 ,  G06F2009/45579

摘要： Operating at least one hypervisor includes running a first hypervisor as a first thread of an underlying operating system, running a second hypervisor as a second thread of the underlying operating system, loading a first guest operating system using the first hypervisor based on the first thread of the underlying operating system, loading a second guest operating system using the second hypervisor based on the second thread of the underlying operating system, and scheduling sharing of resources of the underlying system between the first hypervisor and the second hypervisor according to a scheduler of the underlying operating system, where the first hypervisor and the second hypervisor run independently of each other. The scheduler of the underlying operating system may schedule fractional time shares for the first hypervisor and the second hypervisor to access the same resource.

公开(公告)号：US20090204785A1

公开(公告)日：2009-08-13

申请号：US11982419

申请日：2007-10-31

申请人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

发明人： John S. Yates, JR. ,  David L. Reese ,  Korbin S. Van Dyke ,  T. R. Ramesh ,  Paul H. Hohensee

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30196 ,  G06F9/3802

摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

摘要翻译： 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线识别来自第一页面的执行流程，其相关联的指示符元素指示第一架构。 或执行约定，到第二页，其相关联的指示符元素指示第一个架构或执行约定。 响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

公开(公告)号：US07463865B2

公开(公告)日：2008-12-09

申请号：US11238515

申请日：2005-09-28

申请人： David L. Reese ,  Gregory L. Carlile ,  Curt A. Gray

发明人： David L. Reese ,  Gregory L. Carlile ,  Curt A. Gray

IPC分类号： H04B1/44

CPC分类号： H04B17/0085

摘要： Method and apparatus are provided for compensation of an RF link between a transmitter and amplifier of a communication system. The apparatus comprises a signal source coupled to the transmitter for providing an RF test signal of a first magnitude to the RF link, a test signal measuring apparatus at the RF input of the amplifier for measuring a second magnitude of the test signal reaching the RF input of the amplifier through the RF link, and an electronically adjustable attenuator serially coupled with the RF link and responsive to differences between the first and second magnitudes so as to provide attenuation in an RF communication signal passing into the amplifier from the RF link such that the sum of RF signal loss in the link and the attenuator has a predetermined value.

摘要翻译： 提供了用于补偿通信系统的发射机和放大器之间的RF链路的方法和装置。 该装置包括耦合到发射机的信号源，用于向RF链路提供第一幅度的RF测试信号，在放大器的RF输入处的测试信号测量装置，用于测量到达RF输入的测试信号的第二幅度 通过RF链路的放大器的电子可调衰减器，以及与RF链路串联耦合的电子可调衰减器，并响应于第一和第二幅度之间的差异，以便在从RF链路进入放大器的RF通信信号中提供衰减， 链路中的RF信号损耗和衰减器之和具有预定值。

公开(公告)号：US07013456B1

公开(公告)日：2006-03-14

申请号：US09334530

申请日：1999-06-16

申请人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

发明人： Korbin S. Van Dyke ,  Paul H. Hohensee ,  David L. Reese ,  John S. Yates, Jr. ,  T. R. Ramesh ,  Shalesh Thusoo ,  Gurjeet Singh Saund ,  Stephen C. Purcell ,  Niteen Aravind Patkar

IPC分类号： G06F9/44

CPC分类号： G06F9/45533 ,  G06F9/45541 ,  G06F9/45554

摘要： A method and a computer for performance of the method. While executing a program on a computer, profileable events occurring in the instruction pipeline are detected. The instruction pipeline is directed to record profile information describing the profileable events essentially concurrently with the occurrence of the profileable events. The detecting and recording occur under control of hardware of the computer without software intervention.

摘要翻译： 一种用于执行该方法的方法和计算机。 在计算机上执行程序时，检测到在指令流水线中发生的可轮廓事件。 该指令流水线用于记录描述可概要事件的简档信息，基本上与可概要事件的发生同时发生。 检测和记录在没有软件干预的情况下在计算机硬件的控制下进行。

公开(公告)号：US6064815A

公开(公告)日：2000-05-16

申请号：US207476

申请日：1998-12-08

申请人： Paul H. Hohensee ,  David L. Reese

发明人： Paul H. Hohensee ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3861

摘要： A system for avoiding exceptional conditions during execution of a program comprises an execution enviornment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected. As a result, if the instruction which gave rise to the exception is in a loop or the like, instead of the instruction being processed, the fix-up code will be processed, which will avoid the exception condition.

摘要翻译： 用于在执行程序期间避免异常情况的系统包括用于执行程序的执行环境和修复代码生成子系统。 该程序包括包括一系列指令的指令流，并且执行环境包括例外条件检测器，用于与指令流中的每个指令的执行相关联地检测至少一种预定类型的异常条件。 固定代码生成子系统响应于执行环境检测与指令流中的指令的执行相关联的预定类型的异常情况，用于产生修正代码，该修正代码在被处理时将避免例外情况 并且将指令流中的修正代码替换为检测到至少一个异常条件的指令流中的指令。 结果，如果引起异常的指令处于循环等中，则代替正在处理的指令，将处理修正代码，这将避免异常情况。

公开(公告)号：US07392361B2

公开(公告)日：2008-06-24

申请号：US11049817

申请日：2005-02-03

申请人： David L. Reese ,  Steven R. Chalmer ,  Steven T. McClure ,  Brett D. Niver

发明人： David L. Reese ,  Steven R. Chalmer ,  Steven T. McClure ,  Brett D. Niver

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/00 ,  G06F9/24 ,  G06F15/177 ,  G06F1/24

CPC分类号： G06F9/5016

摘要： Managing memory includes receiving a request for a memory allocation, determining whether the memory allocation is to be maintained when subsequently initializing memory and saving information about the memory allocation to maintain the memory allocation during subsequently initializing memory. Initializing may be performed as part of special reset mode processing. Special reset mode processing may be performed in response to receiving a reset command. The memory may be shared by a plurality of processing units and the reset command may be issued to reset a first processing unit causing reset of the memory and a second processing unit may use a first allocated memory portion that is maintained when initializing the memory as part of processing for the reset command. Saving may include adding an entry to an allocation list associated with the memory, the entry including a location associated with the memory allocation.

摘要翻译： 管理存储器包括接收对存储器分配的请求，确定随后初始化存储器时是否维持存储器分配并且保存关于存储器分配的信息以在随后的初始化存储器期间维持存储器分配。 可以作为特殊复位模式处理的一部分来执行初始化。 可以响应于接收到复位命令而执行特殊复位模式处理。 存储器可以由多个处理单元共享，并且可以发出复位命令以复位导致存储器复位的第一处理单元，并且第二处理单元可以使用在将存储器初始化时保持的第一分配存储器部分作为部分 的复位命令的处理。 保存可以包括向与存储器相关联的分配列表添加条目，该条目包括与该存储器分配相关联的位置。

公开(公告)号：US06954923B1

公开(公告)日：2005-10-11

申请号：US09348317

申请日：1999-07-07

申请人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke

发明人： John S. Yates, Jr. ,  David L. Reese ,  Korbin S. Van Dyke

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/42 ,  G06F9/44

CPC分类号： G06F9/3851 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4486

摘要： An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.

摘要翻译： 一个执行两个指令集的指令处理器。 指令存储在单个地址空间的不同虚拟存储器页面中，并且被编码用于两个不同指令集的计算机，并且使用两种不同的调用约定。 指令处理器根据存储在对应于指令的存储器页的表条目中的第一标志的指示，来解释第一或第二指令集下的指令。 处理器识别何时使用第二数据存储约定将使用第一数据存储约定的指令页面的程序执行转移到指令页，如由表条目中存储的第二标志所指示的，然后调整数据存储内容 的计算机从第一存储惯例到第二数据存储惯例。 历史记录提供了最近执行的指令的分类记录。

公开(公告)号：US06687578B2

公开(公告)日：2004-02-03

申请号：US10113457

申请日：2002-03-28

申请人： Robert G. Lehman ,  David L. Reese

发明人： Robert G. Lehman ,  David L. Reese

IPC分类号： G05D100

CPC分类号： G01C23/00

摘要： An apparatus and method are provided for reducing display clutter and improving the readability of a display by eliminating the necessity of providing separate multifunction control/display units and other similar radio/audio/etc. subsystem CDUs in an aircraft cockpit by providing an interface between the pertinent avionics subsystem (e.g., a satellite data unit (SDU)) and a primary display system (PDS) or other multifunction control/display system. The interface also allows the human-machine interface between the avionics subsystem device and the pilot or aircrew member to be consistent with the human-machine interface for the remainder of the aircraft operations. The interface also allows for automatic detection of the type of interface employed between the avionics subsystem and the primary display system or other multifunction display system, thus allowing the subsystem to automatically adapt to its specific installation environment.

摘要翻译： 提供了一种通过消除提供单独的多功能控制/显示单元和其他类似的无线电/音频等的必要性来减少显示杂波并提高显示器的可读性的装置和方法。 通过提供相关的航空电子系统（例如，卫星数据单元（SDU））和主显示系统（PDS）或其他多功能控制/显示系统之间的接口，在飞行器驾驶舱中的子系统CDU。 该接口还允许航空电子系统设备和飞行员或机组人员之间的人机界面与飞机操作的其余部分的人机接口一致。 该接口还允许自动检测航空电子系统和主显示系统或其他多功能显示系统之间采用的接口类型，从而允许子系统自动适应其特定的安装环境。

公开(公告)号：US5765206A

公开(公告)日：1998-06-09

申请号：US608571

申请日：1996-02-28

申请人： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

发明人： Paul H. Hohensee ,  David Dice ,  Robert G. Vandette ,  David L. Reese

IPC分类号： G06F9/455 ,  G06F9/318 ,  G06F9/34 ,  G06F12/10

CPC分类号： G06F9/45537 ,  G06F12/1036 ,  G06F12/109 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/34

摘要： A processor processes a segmented to linear virtual address conversion instruction to convert segmented virtual addresses in a segmented virtual address space to a linear virtual address in a linear virtual address space. The segmented virtual address space comprises a plurality of segments each identified by a segment identifier, each segment comprising at least one page identified by a page identifier. The linear virtual address space includes a plurality of pages each identified by a page identifier. In processing the segmented to linear virtual address conversion instruction, the processor uses a plurality of segmented to linear virtual address conversion descriptors, each associated with a page in the segmented virtual address space, each segmented to linear virtual address conversion descriptor identifying the page identifier of one of the pages in the linear virtual address space. The segmented to linear virtual address conversion instruction includes a segmented virtual address identifier in the segmented virtual address space. In processing the segmented to linear virtual address conversion instruction, the processor uses the segmented virtual address identifier in the segmented to linear virtual address conversion instruction to select one of the segmented to linear virtual address conversion descriptors. After selecting a segmented to linear virtual address conversion descriptor, the processor uses the page identifier of the linear virtual address space from the selected segmented to linear virtual address conversion descriptor and the segmented virtual address identifier in the segmented to linear virtual address conversion instruction in generating a virtual address in the linear virtual address space.

摘要翻译： 处理器处理分段到线性虚拟地址转换指令，以将分段虚拟地址空间中的分段虚拟地址转换为线性虚拟地址空间中的线性虚拟地址。 分割的虚拟地址空间包括多个片段，每个片段由片段标识符标识，每个片段包括由页面标识符标识的至少一个页面。 线性虚拟地址空间包括由页面标识符标识的多个页面。 在处理分段到线性虚拟地址转换指令时，处理器使用多个分段到线性的虚拟地址转换描述符，每个分割到线性虚拟地址转换描述符与分段的虚拟地址空间中的一个页面相关联，每个划分为线性虚拟地址转换描述符， 线性虚拟地址空间中的一个页面。 分段到线性虚拟地址转换指令包括分段虚拟地址空间中的分段虚拟地址标识符。 在处理分段到线性虚拟地址转换指令时，处理器使用分段到线性虚拟地址转换指令中的分段虚拟地址标识符来选择分段到线性虚拟地址转换描述符之一。 在选择分段到线性虚拟地址转换描述符之后，处理器使用从所选择的分段到线性虚拟地址转换描述符的线性虚拟地址空间的页面标识符和分段到线性虚拟地址转换指令中的分段虚拟地址标识符，以生成 线性虚拟地址空间中的虚拟地址。

公开(公告)号：US08121828B2

公开(公告)日：2012-02-21

申请号：US11003768

申请日：2004-12-02

申请人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

发明人： John S. Yates, Jr. ,  David L. Reese ,  Paul H. Hohensee ,  Stephen C. Purcell ,  Korbin S. Van Dyke

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

摘要翻译： 计算机具有能够执行两个指令集架构（ISA）的指令流水线电路。 二进制翻译器至少将计算机程序的选定部分从ISA的较低性能转换为ISA的更高性能的一个。 当即将执行在低性能ISA中编码的程序区域时，硬件启动查询，以确定是否存在更高性能的转换。 如果是这样，即将执行的指令被中止，并且控制转移到更高性能的转换。 执行较高性能的翻译后，在排除后的指令下游的一个点重新建立较低性能区域的执行，在逻辑上相当于在较低性能区域的代码被允许的情况下 继续。