Print media registration using active tracking of idler rotation
    11.
    发明授权
    Print media registration using active tracking of idler rotation 有权
    使用主动跟踪惰轮旋转打印介质注册

    公开(公告)号:US07243917B2

    公开(公告)日:2007-07-17

    申请号:US10855451

    申请日:2004-05-27

    IPC分类号: B65H7/02

    摘要: More accurately correcting sheet position and skew in a desired print media sheet trajectory in a printer paper path, with a registration system including sheet drive nips defined by laterally spaced and differentially driven elastomer surfaced frictional sheet drive rollers and mating undriven idler rollers have a non-slip rotational sheet engagement. The undriven idler rollers have rotary encoders producing encoder signals corresponding to their rotation by a sheet in the nip, which encoder signals are provided to a controller for the registration system to control forward and differential drive motor systems for the sheet drive rollers so as to substantially correct for errors in the desired trajectory of said sheet by sheet drag forces acting on the elastomer surfaced sheet drive rollers in the sheet drive nips.

    摘要翻译: 在打印机纸张路径中更准确地校正纸张位置和期望的打印介质纸张轨迹中的偏斜,其中包括由横向间隔开的差分驱动的弹性体表面的摩擦片材驱动辊和配合的未驱动的惰辊定义的纸张驱动辊隙的配准系统具有非 - 滑动旋转片接合。 未驱动的惰辊具有旋转编码器,其产生对应于其在辊隙中的片材的旋转的编码器信号,该编码器信号被提供给用于配准系统的控制器,以控制片材驱动辊的前进和差速驱动马达系统, 纠正作用在片材驱动夹头中的弹性体表面的片材驱动辊上的所述片材牵引力的期望轨迹中的误差。

    High voltage level translator
    12.
    发明授权
    High voltage level translator 失效
    高电压电平转换器

    公开(公告)号:US07019560B2

    公开(公告)日:2006-03-28

    申请号:US10263512

    申请日:2003-01-13

    IPC分类号: H03K19/0175 H03K19/094

    摘要: A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the transducer and a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET's threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed. The control circuit reduces switching time and reduces current spikes in the power supplies to the chip.

    摘要翻译: 用于控制压电换能器的电路包括具有栅电极的N沟道FET,耦合到高电压信号源Vpp的漏极,其中Vpp是正向脉冲串,以及耦合到输出Vcntr1的源电极用于控制 传感器和充电电路,响应于低电压输入信号Vpp_sel,用于将FET栅极充电到大于FET阈值电压的偏置电压,同时Vpp接近零伏,并且用于在Vpp斜坡时保持FET栅极上的偏置电压 达到大于偏置电压的值,直到Vpp_sel被去除。 控制电路减少了开关时间,并减少了芯片电源的电流尖峰。

    Local display bus architecture and communications method for Raster
display
    14.
    发明授权
    Local display bus architecture and communications method for Raster display 失效
    本地显示总线架构和通讯方式,用于光栅显示

    公开(公告)号:US5185599A

    公开(公告)日:1993-02-09

    申请号:US555979

    申请日:1990-07-23

    摘要: A high performance graphics display system for use as an engineering workstation includes a compact method of generating vectors and transmitting addresses for same from a picture processor to frame buffer control circuitry for writing or reading pixel values along the vector in the frame buffer. The system uses a multiplexed address/data bus. Off-screen memory in communication with the picture processor is used to store pixel data read along vectors in the frame buffer preceding writing a vector so that the original data can be restored when the written vector is moved or removed. Vectors are encoded by the picture processor as a first word containing the address of the beginning point of the vector and major axis and X and Y direction bits to indicate the vector's direction. A second word includes a minor axis bit, indicating whether the next pixel to be written or read is on or off the major axis, in the direction indicated for such axis in the first word. The first word also includes a hesitate bit indicating whether the first pixel of a vector is to be written or read. The system is configured in pipe stages with a FIFO at each stage controlled by a hold signal that is pipelined from downstream stages in a direction opposite the pipelined data flow.

    摘要翻译: 用作工程工作站的高性能图形显示系统包括一种紧凑的方法,用于产生矢量并将图像处理器的地址从图像处理器发送到帧缓冲器控制电路,用于沿着帧缓冲器中的向量写入或读取像素值。 系统使用复用的地址/数据总线。 与图像处理器通信的离屏存储器用于存储在写入向量之前沿着帧缓冲器中的向量读取的像素数据,使得当写入的向量被移动或移除时可以恢复原始数据。 向量由图像处理器编码为包含向量和长轴的起始点的地址的第一个字,以及指示向量方向的X和Y方向位。 第二个字包括一个短轴位,指示要写入或读取的下一个像素是否在长轴上或在第一个字中针对该轴指示的方向上。 第一个字还包括一个犹豫的位,指示矢量的第一个像素是要被写入还是读取。 该系统配置在管道阶段,每个阶段的FIFO由保持信号控制,保持信号从流水线数据流的相反方向从下游阶段流水线化。

    Image frame buffer access speedup by providing multiple buffer
controllers each containing command FIFO buffers
    15.
    发明授权
    Image frame buffer access speedup by providing multiple buffer controllers each containing command FIFO buffers 失效
    图像帧缓冲区访问加速通过提供多个缓冲区控制器,每个包含命令FIFO缓冲区

    公开(公告)号:US5109520A

    公开(公告)日:1992-04-28

    申请号:US129897

    申请日:1987-11-16

    申请人: David L. Knierim

    发明人: David L. Knierim

    CPC分类号: G09G5/393 G09G5/395 G09G5/022

    摘要: A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

    摘要翻译: 帧缓冲存储器控制器允许快速图像更新,同时保持屏幕刷新数据流速。 一帧缓冲存储器控制器控制每个像素包括一个或多个帧缓冲存储器芯片的一个或多个像素深度列。 每个帧缓冲存储器控制器在显示处理器总线上侦听寻址到其控制下的像素或存储器芯片的读取,写入或读取 - 修改 - 写入命令。 这样的命令以及相关联的地址和数据被存储在先入先出(FIFO)缓冲器中,以在第一空闲存储器循环期间执行。

    Method and circuit for computing reciprocals
    16.
    发明授权
    Method and circuit for computing reciprocals 失效
    用于计算倒数的方法和电路

    公开(公告)号:US4823301A

    公开(公告)日:1989-04-18

    申请号:US111965

    申请日:1987-10-22

    申请人: David L. Knierim

    发明人: David L. Knierim

    摘要: A circuit produces an output binary floating point number approximating with high accuracy the inverse of an input binary floating point number D in accordance with the expression (1/D).apprxeq.[(1/A)-C]+[C-(B/A.sup.2)], where the number A is a low accuracy approximation of D, and B is substantially equal to D-A. C is a number selected for each value of A such that the exponents of quantities [(1/A)-C] and [C-(B/A.sup.2)] are equal to the exponent of the quantity 1/2A. Quantities [(1/A)-C] and [C-(B/A.sup.2)] are produced by lookup tables and summed to provide an approximation of 1/D.

    摘要翻译: 根据表达式(1 / D)APPROX [(1 / A)-C] + [C-(B / D)),电路产生高精度近似输入二进制浮点数D的输出二进制浮点数, A2)],其中数字A是D的低精度近似,并且B基本上等于DA。 C是为每个值A选择的数字,使得[(1 / A)-C]和[C-(B / A2)]的指数等于数量1 / 2A的指数。 通过查找表产生数量[(1 / A)-C]和[C-(B / A2)],并求和以提供1 / D的近似值。

    Oleophobic ink jet orifice plate
    19.
    发明授权
    Oleophobic ink jet orifice plate 有权
    疏油喷墨孔板

    公开(公告)号:US08615881B2

    公开(公告)日:2013-12-31

    申请号:US13467393

    申请日:2012-05-09

    申请人: David L. Knierim

    发明人: David L. Knierim

    IPC分类号: B21D53/76 B23P17/00 B41J2/015

    摘要: A method for forming a print head having a plurality of reentrant structures to reduce wetting of the print head surface by the ink during use, and a resulting structure. The method can include the use of a single photosensitive layer to form plurality of reentrant structures, each having a pillar and a cap which overhangs the pillar. A plurality of print head nozzles can also be formed during the formation of the reentrant structures. Embodiments can include the formation of pillars, caps, and nozzles using three different masks, two different masks, or a single mask.

    摘要翻译: 一种用于形成具有多个可折入结构的打印头的方法,以减少在使用过程中油墨对打印头表面的润湿,以及所得到的结构。 该方法可以包括使用单个感光层来形成多个可重入结构,每个具有一个柱和一个突出在支柱上的帽。 在形成折返结构期间也可以形成多个打印头喷嘴。 实施例可以包括使用三个不同掩模,两个不同掩模或单个掩模形成支柱,帽和喷嘴。