摘要:
A method for displaying a result of area extraction processing of dividing a target image into a foreground area and a background area includes a result acquisition step of acquiring a result of the area extraction processing on the target image, an extraction result image generation step of acquiring an extraction result image representing an estimated foreground area or an estimated background area estimated by the area extraction processing or a boundary between the estimated foreground area and the estimated background area, based on the acquired result, and a display step of generating a composite image by combining the extraction result image with the target image, and displaying the composite image on a display device. The extraction result image generation step includes a color extraction step and a color determination step.
摘要:
Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.
摘要:
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要:
The present invention provides a character highlighting control apparatus including a highlighting degree controller and an image quality converter, wherein a character part and a background part are in an image to be displayed on a display screen. The highlighting degree controller is configured to control a panel driver to increase a luminance of a pixel in the character part. The image quality converter is configured to decrease a luminance of a pixel in the background part when the luminance of the pixel in the character part is increased.
摘要:
The present invention provides a character highlighting control apparatus including a character pixel extractor and a highlighting degree controller. The character pixel extractor is configured to extract a pixel corresponding to a character part from input image data. The highlighting degree controller is configured to carry out control in such a way that a maximum emission luminance of a display device is linked with input image data, to thereby selectively increase an emission luminance of an extracted pixel on a display screen and avoid increase of an emission luminance of a background part on the display screen.
摘要:
An apparatus includes: a division unit configured to divide image data into a plurality of blocks each being composed of a plurality of pixels; a detection unit configured to detect a most frequent color for each of the blocks; a calculation unit configured to calculate an occupancy rate of the most frequent color for each of the blocks; and a generation unit configured to generate data by changing between a block composed of at least a low-resolution pixel and a block composed of low- and high-resolution pixels superimposed with each other, based on the most frequent color occupancy rate.
摘要:
A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.
摘要:
A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.
摘要:
A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.
摘要:
A video processing device includes a sprite rendering processor in connection with a display buffer (e.g. line buffers) and an alpha table. The sprite rendering processor alternately performs first rendering based on sprite attribute data and second rendering based on alpha attribute data. The first rendering is performed via alpha blending on video data of sprites, rendering-destination video data of the display buffer, and rendering-destination alpha data of the alpha buffer which are produced via the second rendering with the alpha buffer, thus producing resultant video data, which is written over rendering-destination video data in the display buffer. One type of sprite is connected with at least one alpha table which describes alpha data ranging from perfect transparency and perfect non-transparency and which is optimized to demonstrate an anti-aliasing effect on the boundary of a colored region of each sprite on the screen of a visual display.