利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

33 条记录 (耗时 0.036 秒)

    METHOD AND SYSTEM FOR EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE
    11.
    发明申请
    METHOD AND SYSTEM FOR EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE 失效
    用于早期指导文本操作的方法和系统存储比较对象避免

    公开(公告)号：US20090210675A1

    公开(公告)日：2009-08-20

    申请号：US12034042

    申请日：2008-02-20

    申请人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

    发明人： Khary J. Alexander ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

    摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

    摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

    Modular binary multiplier for signed and unsigned operands of variable widths
    12.
    发明授权
    Modular binary multiplier for signed and unsigned operands of variable widths 有权
    具有可变宽度的有符号和无符号操作数的模块二进制乘法器

    公开(公告)号：US07490121B2

    公开(公告)日：2009-02-10

    申请号：US11749239

    申请日：2007-05-16

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

    摘要翻译： 在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

    Modular binary multiplier for signed and unsigned operands of variable widths
    13.
    发明授权
    Modular binary multiplier for signed and unsigned operands of variable widths 有权
    具有可变宽度的有符号和无符号操作数的模块二进制乘法器

    公开(公告)号：US07853635B2

    公开(公告)日：2010-12-14

    申请号：US11749224

    申请日：2007-05-16

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    IPC分类号： G06F7/38 ,  G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

    摘要翻译： 超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

    Modular binary multiplier for signed and unsigned operands of variable widths
    14.
    发明授权
    Modular binary multiplier for signed and unsigned operands of variable widths 有权
    具有可变宽度的有符号和无符号操作数的模块二进制乘法器

    公开(公告)号：US07266580B2

    公开(公告)日：2007-09-04

    申请号：US10435976

    申请日：2003-05-12

    申请人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    发明人： Fadi Y. Busaba ,  Steven R. Carlough ,  David S. Hutton ,  Christopher A. Krygowski ,  John G. Rell, Jr. ,  Sheryll H. Veneracion

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F7/5332 ,  G06F9/30014 ,  G06F2207/3816

    摘要： A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.

    摘要翻译： 本文中讨论了用于对具有各种长度的有符号和无符号操作数进行二进制乘法的方法和装置。 这是一个概念，可以分为两部分，第一部分是乘法硬件本身，紧凑型，小于满量程的乘法器，在乘数上使用Booth或其他类型的重新编码方法，以减少每个部分产品的数量 扫描和实现，使得具有大操作数的乘法运算可以被分解成适合于该中型乘法器的操作子组，其结果（这里称为模块化产品）可以针织在一起以形成正确的， 完成品。 该概念的第二部分是用于将操作数分成子组并将数据和控制信号输入到乘法器的支持硬件，以及用于对准和组合模块化产品以获得最终产品的算法和装置。 用于获得由操作指定的结果的这些算法可以与可以使用乘法器的支持硬件一样变化，使得该乘法器是非常灵活和强大的设计。

    Early instruction text based operand store compare reject avoidance
    15.
    发明授权
    Early instruction text based operand store compare reject avoidance 失效
    早期指令文本操作数存储比较拒绝回避

    公开(公告)号：US08195924B2

    公开(公告)日：2012-06-05

    申请号：US13050484

    申请日：2011-03-17

    申请人： Khary J. Alexander ,  Fadi Y. Basuba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

    发明人： Khary J. Alexander ,  Fadi Y. Basuba ,  Bruce C. Giamei ,  David S. Hutton ,  Chung-Lung K. Shum

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3826 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

    摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

    摘要翻译： 提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。 该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。 该系统还包括监视指令流的延迟逻辑。 延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。 响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

    System and method for providing a common instruction table
    18.
    发明授权
    System and method for providing a common instruction table 有权
    用于提供通用指令表的系统和方法

    公开(公告)号：US07895538B2

    公开(公告)日：2011-02-22

    申请号：US12033974

    申请日：2008-02-20

    申请人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

    发明人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/68

    摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.

    摘要翻译： 系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。 该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。 该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。 对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

    SYSTEM AND METHOD FOR PROVIDING A COMMON INSTRUCTION TABLE
    19.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING A COMMON INSTRUCTION TABLE 有权
    用于提供通用指令表的系统和方法

    公开(公告)号：US20090210387A1

    公开(公告)日：2009-08-20

    申请号：US12033974

    申请日：2008-02-20

    申请人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

    发明人： David S. Hutton ,  James J. Bonanno ,  Michael P. Mullen ,  Chung-Lung Kevin Shum

    IPC分类号： G06F17/30

    CPC分类号： G06F17/5045 ,  G06F2217/68

    摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.

    摘要翻译： 系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。 该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。 该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。 对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY
    20.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY 审中-公开
    用于最小化分支预测延迟的方法，系统和计算机程序产品

    公开(公告)号：US20090217017A1

    公开(公告)日：2009-08-27

    申请号：US12037137

    申请日：2008-02-26

    申请人： Khary J. Alexander ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  John W. Ward, III

    发明人： Khary J. Alexander ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  John W. Ward, III

    IPC分类号： G06F9/30

    CPC分类号： G06F9/381 ,  G06F9/3806 ,  G06F9/3814

    摘要： A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB.

    摘要翻译： 提供了一种用于在流水线计算机处理环境中最小化分支预测延迟的方法，系统和计算机程序产品。 该方法包括利用转移指令地址和存储在分支目标缓冲器（BTB）中的对应目标地址来检测分支回路。 该方法还包括将分支循环读取到预解码指令缓冲器中，并对分支循环进行限定循环锁定。 该方法还包括将形成分支循环的指令流锁定在预解码指令缓冲器中，并且处理来自缓冲器的限定分支循环指令并且断电与BTB相关联的指令获取和分支预测逻辑（BPL）。