公开(公告)号：US07333905B2

公开(公告)日：2008-02-19

申请号：US11383570

申请日：2006-05-16

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R29/02

CPC分类号： G01R29/02 ,  G01R31/31725 ,  G01R31/31726

摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

摘要翻译： 所公开的方法和装置测量时钟信号的占空比。 可变占空比电路从时钟信号发生器接收时钟信号。 可变占空比电路根据其接收的占空比指数值来调整时钟信号的占空比。 可变占空比电路将占空比调整的时钟信号提供给分频器电路。 该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。 然后，该装置从最大频率确定占空比调整的时钟信号的占空比。

公开(公告)号：US07917795B2

公开(公告)日：2011-03-29

申请号：US12014501

申请日：2008-01-15

申请人： David William Boerstler ,  Eskinder Hailu ,  Byron Lee Krauter ,  Kazuhiko Miki ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Byron Lee Krauter ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/00 ,  G06F1/04 ,  H03K19/096 ,  H03K5/22 ,  H03K7/08 ,  H03K9/08 ,  H03L7/06 ,  G01R23/00 ,  G01M19/00

CPC分类号： G06F1/10 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

公开(公告)号：US20070300082A1

公开(公告)日：2007-12-27

申请号：US11471819

申请日：2006-06-21

申请人： Yosuke Muraki ,  Tetsuji Tamura ,  Iwao Takiguchi ,  Makoto Aikawa ,  Eskinder Hailu ,  Byron Lee Krauter ,  Stephen Douglas Weitzel ,  Jieming Qi ,  Kazuhiko Miki ,  David William Boerstler ,  Gilles Gervais ,  Kirk David Peterson ,  Robert Walter Berry ,  Sang Hoo Dhong

发明人： Yosuke Muraki ,  Tetsuji Tamura ,  Iwao Takiguchi ,  Makoto Aikawa ,  Eskinder Hailu ,  Byron Lee Krauter ,  Stephen Douglas Weitzel ,  Jieming Qi ,  Kazuhiko Miki ,  David William Boerstler ,  Gilles Gervais ,  Kirk David Peterson ,  Robert Walter Berry ,  Sang Hoo Dhong

IPC分类号： G06F1/00

CPC分类号： G06F1/04

摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

摘要翻译： 用于向微处理器提供电源电压的技术。 在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。 在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

公开(公告)号：US08041537B2

公开(公告)日：2011-10-18

申请号：US12163081

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G04F1/00

CPC分类号： H03K5/1565

摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.

摘要翻译： 本公开的实施例提供了用于时钟占空比测量的系统和方法。 时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。 电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。 此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。 电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。 然后，使用第一，第二，第三和第四电压来计算时钟的占空比。

公开(公告)号：US07646177B2

公开(公告)日：2010-01-12

申请号：US12347853

申请日：2008-12-31

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H02J7/00

CPC分类号： G01R31/31727

摘要： A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit may apply a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. The design structure may specify that control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

摘要翻译： 用于片上占空比测量系统的设计结构可以体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构可以体现测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比的装置。 设计结构可以指定DCM电路包括由电荷泵驱动的电容器，并且参考时钟信号驱动电荷泵。 设计结构可以指定时钟电路在多个已知占空比值之间改变参考时钟信号的占空比。 该设计结构可以指定DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路可以通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号的占空比的新电压值。 设计结构可以指定控制软件访问数据存储以确定测试时钟信号对应的占空比。

公开(公告)号：US20090322311A1

公开(公告)日：2009-12-31

申请号：US12163166

申请日：2008-06-27

申请人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

发明人： Jieming Qi ,  Eskinder Hailu ,  David William Boerstler ,  Masaaki Kaneko

IPC分类号： G01R23/02 ,  G06F1/04

CPC分类号： G06F1/08

摘要： Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.

摘要翻译： 本公开的实施例提供了在环路外部使用PLL和高频发生器以获得分频器的fmax的系统和方法。 PLL环路中的分频器由VCO馈送，其工作范围的特征在于测量PLL锁定范围。 相同分频器的相同拷贝在PLL环路外部使用，并由较高频率的时钟馈送。 高频时钟由VCO的多相产生。 通过对来自两个分频器的输出进行表征，获得分频器的fmax。

公开(公告)号：US07620126B2

公开(公告)日：2009-11-17

申请号：US11236658

申请日：2005-09-27

申请人： David William Boerstler ,  Matthew E. Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Wayne Riley

发明人： David William Boerstler ,  Matthew E. Fernsler ,  Eskinder Hailu ,  Jieming Qi ,  Mack Wayne Riley

IPC分类号： H03D3/18

CPC分类号： H03L7/093 ,  H03L7/095

摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.

摘要翻译： 公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

公开(公告)号：US20090112555A1

公开(公告)日：2009-04-30

申请号：US12347853

申请日：2008-12-31

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： G01R31/31727

摘要： A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit may apply a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. The design structure may specify that control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

摘要翻译： 用于片上占空比测量系统的设计结构可以体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构可以体现测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比的装置。 设计结构可以指定DCM电路包括由电荷泵驱动的电容器，并且参考时钟信号驱动电荷泵。 设计结构可以指定时钟电路在多个已知占空比值之间改变参考时钟信号的占空比。 该设计结构可以指定DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路可以通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 设计结构可以指定控制软件访问数据存储以确定测试时钟信号对应的占空比。

公开(公告)号：US20080174345A1

公开(公告)日：2008-07-24

申请号：US11931879

申请日：2007-10-31

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K21/16

CPC分类号： G01R29/02 ,  G01R31/31725 ,  G01R31/31726

摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

摘要翻译： 所公开的方法和装置测量时钟信号的占空比。 可变占空比电路从时钟信号发生器接收时钟信号。 可变占空比电路根据其接收到的占空比指数值来调整时钟信号的占空比。 可变占空比电路将占空比调整的时钟信号提供给分频器电路。 该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。 然后，该装置从最大频率确定占空比调整的时钟信号的占空比。

公开(公告)号：US07350095B2

公开(公告)日：2008-03-25

申请号：US11082973

申请日：2005-03-17

申请人： David William Boerstler ,  Eskinder Hailu ,  Byron Lee Krauter ,  Kazuhiko Miki ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Byron Lee Krauter ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F1/04

CPC分类号： G06F1/10 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。