公开(公告)号：US07528461B2

公开(公告)日：2009-05-05

申请号：US11423335

申请日：2006-06-09

Applicant: Davide Patti ,  Sebastiano Aparo

Inventor： Davide Patti ,  Sebastiano Aparo

IPC: H01L29/73

CPC classification number: H01L29/7302 ,  H01L29/0692 ,  H01L29/866

Abstract: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate. An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.

Abstract translation: 双极功率晶体管不包括电连接在基极和集电极之间的齐纳二极管的集成，以限制集电​​极电压。 功率晶体管形成在衬底中，并且包括沿衬底的周边形成P-N结的均衡扩散和辅助扩散。 均衡传导层与用于电短路P-N结的均衡扩散和辅助扩散接触。

公开(公告)号：US20070013032A1

公开(公告)日：2007-01-18

申请号：US11423335

申请日：2006-06-09

Applicant: Davide Patti ,  Sebastiano Aparo

Inventor： Davide Patti ,  Sebastiano Aparo

IPC: H01L27/082

CPC classification number: H01L29/7302 ,  H01L29/0692 ,  H01L29/866

Abstract: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.

Abstract translation: 双极功率晶体管不包括电连接在基极和集电极之间的齐纳二极管的集成，以限制集电​​极电压。 功率晶体管形成在衬底中，并且包括沿着衬底的周边形成P-N结的均衡扩散和辅助扩散。均衡传导层与用于电短路P-N结的均衡扩散和辅助扩散接触。

公开(公告)号：US07126167B2

公开(公告)日：2006-10-24

申请号：US10888789

申请日：2004-07-09

Applicant: Davide Patti ,  Antonino Torres

Inventor： Davide Patti ,  Antonino Torres

IPC: H01L29/43

CPC classification number: H01L29/7395

Abstract: A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.

Abstract translation: 一种集成在由第一导电类型的半导体衬底中的第一导电类型的半导体层的器件，其包括电压控制电阻结构和IGBT器件的第二导电类型的半导体层，其中所述电阻结构包括至少一个第一 围绕半导体层的一部分的导电性的类型。

公开(公告)号：US06815798B2

公开(公告)日：2004-11-09

申请号：US10439277

申请日：2003-05-15

Applicant: Natale Aiello ,  Davide Patti

Inventor： Natale Aiello ,  Davide Patti

IPC: H01L2900

CPC classification number: H01L27/0676 ,  H01L29/94

Abstract: A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.

公开(公告)号：US07675135B2

公开(公告)日：2010-03-09

申请号：US11575227

申请日：2005-09-12

Applicant: Davide Patti ,  Giuditta Settanni

Inventor： Davide Patti ,  Giuditta Settanni

IPC: H01L23/58

CPC classification number: H01L29/0615

Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (α) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

Abstract translation: 可以有效地防止在必须实现集成装置的主结（P_tub 1，（P_tub2，...））的周边高压环延伸注入区域（RHV）的中断时产生的不稳定性和相关缺点，这一重要结果 通过非常简单的方法实现：每当必须产生高压环延伸的中断（I）时，沿着与周边注入区域的共同正交方向在其上没有实现直线，相反，窄的中断是 倾斜或倾斜地定位在周边高压环延伸的宽度上，在直线中断的情况下，倾斜角（α）通常可以在30度和60度之间，更优选地在45度或更接近于它。 ，当实现周边高压环延伸区域时，通过将其从掺杂剂注入掩蔽来产生窄中断。

公开(公告)号：US20080237773A1

公开(公告)日：2008-10-02

申请号：US11575227

申请日：2005-09-12

Applicant: Davide Patti ,  Giuditta Settanni

Inventor： Davide Patti ,  Giuditta Settanni

IPC: H01L21/265 ,  H01L29/36

CPC classification number: H01L29/0615

Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (α) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

Abstract translation: 可以有效地防止在必须实现集成装置的主结（P_tub 1，（P_tub 2，...）的周边高压环延伸注入区域（RHV）的中断时产生的不稳定性和相关缺点，这很重要 结果是通过非常简单的方法实现的：每当必须产生高压环延伸的中断（I）时，沿着与周边注入区域的共同正交方向在其上没有实现直线，相反，窄中断 在圆周高压环延伸部的宽度上倾斜或倾斜地定义，在直线中断的情况下，倾斜角（α）通常可以包含30度到60度之间，更优选地在45度附近。 当然，当实现周边高电压环延伸区域时，通过将其从掺杂剂注入掩蔽来产生窄的中断。

公开(公告)号：US06774061B2

公开(公告)日：2004-08-10

申请号：US09811159

申请日：2001-03-15

Applicant: Salvatore Coffa ,  Davide Patti

Inventor： Salvatore Coffa ,  Davide Patti

IPC: H01L21336

CPC classification number: H01L21/28273 ,  Y10S438/962

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract translation: 公开了一种在氧化物层中形成硅纳米晶体薄层的工艺。 该方法包括在半导体衬底上将衬底的第一部分热氧化成氧化物层，在氧化物层内形成硅离子，以及热处理硅离子以成为硅纳米晶体的薄层。 在本发明的方法中，硅离子的形成是通过以0.1keV至7keV，优选1至5keV之间的离子化能量将硅离子离子注入氧化物中。 这允许硅原子在比其他可能的温度更低的温度下聚结。 另外，可以通过在多于一个能级执行多于一次的注入来形成多于一层的纳米晶体。 本发明的实施例可用于形成具有非常小尺寸的非常高质量的非易失性存储器件。

公开(公告)号：US06590272B2

公开(公告)日：2003-07-08

申请号：US09991555

申请日：2001-11-21

Applicant: Davide Patti

Inventor： Davide Patti

IPC: H01L2900

CPC classification number: H01L28/20 ,  H01L27/0802 ,  H01L29/8605

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

Abstract translation: 一种用于半导体电阻元件的结构，特别适用于具有n型高浓度衬底，n型第一外延层，布置在所述第一外延层上的p型区域的功率元件，从而形成 电阻元件本体，在所述第一外延层上生长以使p型区域成为掩埋区域的n型第二外延层和相对于第二外延级别具有较高浓度的n型附加层，定位 在嵌入式区域。 提供适于为电阻器制造低电阻率深触点的p型低电阻率区域。 掩埋区域可以通过在其主要延伸方向上基本均匀的发展来实现，或者在其长度的一部分上呈现边缘连续性的相邻子区域的结构。 以这种方式，可以在所施加的电压的所有范围内呈现基本上线性的电阻元件，或者施加的电压增加时呈现电阻值的显着增加的电阻元件。 这一切都具有选择性地改变在增加之前显示的电阻值的附加可能性。

公开(公告)号：US06548863B2

公开(公告)日：2003-04-15

申请号：US09973960

申请日：2001-10-09

Applicant: Davide Patti

Inventor： Davide Patti

IPC: H01L31113

CPC classification number: H01L29/0852 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7816 ,  H01L29/7824

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

公开(公告)号：US6069399A

公开(公告)日：2000-05-30

申请号：US79827

申请日：1998-05-15

Applicant: Davide Patti

Inventor： Davide Patti

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/73 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66303 ,  H01L29/0804 ,  H01L29/7304

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers. The emitter buried region and the sinker emitter region delimit in each emitter finger pairs of sections which are mutually spaced and delimit between one another a central region of the epitaxial layer. The sinker emitter region of each pair of sections of an emitter finger extend in the vicinity of mutually facing edges of the emitter buried region of the pair of sections.

Abstract translation: 一种晶体管，包括具有第一导电类型的外延层，具有第二导电类型的基极掩埋区域和具有第二导电类型的沉降片基极区域，从晶体管的主表面延伸到基底掩埋区域， 与基极掩埋区一起，发射极指在外延层中。 晶体管还包括具有第一导电类型的发射极掩埋区和高于外延层的掺杂水平的掺杂水平。 发射极掩埋区域在与基底掩埋区域相邻的位置嵌入在外延层中。 具有第一导电类型和掺杂水平的沉降弧发射极区域，其高于外延层的掺杂水平并且从发射极指状物内部的主表面延伸到发射极掩埋区域。 发射极掩埋区域和沉陷弧发射极区域在每个发射极指状物中限定，这些区域彼此间隔开并且在彼此之间限定外延层的中心区域。 发射极指的每对部分的沉降弧发射极区域在该对部分的发射极掩埋区域的相互面对的边缘附近延伸。