公开(公告)号：US06578059B1

公开(公告)日：2003-06-10

申请号：US09169669

申请日：1998-10-10

申请人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

发明人： Jerome C. Huck ,  Peter Markstein ,  Glenn T. Colon-Bonet ,  Alan H. Karp ,  Roger Golliver ,  Michael Morrison ,  Gautam B. Doshi

IPC分类号： G06F748

CPC分类号： G06F9/3865 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/49942 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30123 ,  G06F2207/382

摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

公开(公告)号：US06301705B1

公开(公告)日：2001-10-09

申请号：US09164327

申请日：1998-10-01

申请人： Gautam B. Doshi ,  Peter Markstein ,  Alan H. Karp ,  Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Michael Morrison

发明人： Gautam B. Doshi ,  Peter Markstein ,  Alan H. Karp ,  Jerome C. Huck ,  Glenn T. Colon-Bonet ,  Michael Morrison

IPC分类号： G06F945

CPC分类号： G06F9/3865 ,  G06F9/3842

摘要： The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.

摘要翻译： 本发明一般涉及用于支持对包括非投机和推测指令的中央处理单元（CPU）的指令集的推测性执行的系统和方法。 根据本发明的一个方面，一种方法包括以下步骤：评估程序的指令以确定各个指令是推测性还是非推测性的，并且评估每个推测性指令以确定其是否产生异常。 对于产生异常的每个推测性指令，该方法然后将延迟异常令牌（DET）编码为CPU的寄存器的未使用的寄存器值。 根据本发明的另一方面，提供了一种系统，该系统包括被配置为评估指令集的指令以确定各个指令是推测性还是非推测性的电路。 系统还包括被配置为评估每个推测性指令以确定其是否产生异常的电路。 最后，系统还包括被配置为将延迟异常令牌（DET）编码为（CPU的）寄存器的未使用寄存器值的电路。

公开(公告)号：US5329176A

公开(公告)日：1994-07-12

申请号：US137902

申请日：1993-09-29

申请人： Robert H. Miller, Jr. ,  Jeffry D. Yetter ,  Glenn T. Colon-Bonet ,  Robert J. Martin

发明人： Robert H. Miller, Jr. ,  Jeffry D. Yetter ,  Glenn T. Colon-Bonet ,  Robert J. Martin

IPC分类号： G06F7/50 ,  G06F7/501 ,  H03K19/094 ,  H03K19/096 ,  H03K19/21 ,  H03K19/017

CPC分类号： G06F7/5016 ,  H03K19/094 ,  H03K19/0966 ,  H03K19/215

摘要： A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.

摘要翻译： 为具有级联自定时动态逻辑门的逻辑块提供时钟系统和方法。 动态逻辑门并行预充电，并对矢量输入进行自定时逻辑评估，以得出矢量输出。 评估完成检测器监视逻辑块的输出，并确定矢量输出何时有效。 边缘检测器检测任意周期性定时信号的上升沿和下降沿。 最后，由边缘检测器设置逻辑块时钟发生器并由评估完成检测器复位，以便向逻辑块提供预充电信号，从而定义相应的预充电周期，并且提供用于自适应逻辑评估的评估周期 逻辑块。 在具体实现中，逻辑评估的速度是系统时钟速度的两倍。