Processor architecture having two or more floating-point status fields
    1.
    发明授权
    Processor architecture having two or more floating-point status fields 有权
    具有两个或多个浮点状态字段的处理器架构

    公开(公告)号:US06370639B1

    公开(公告)日:2002-04-09

    申请号:US09169482

    申请日:1998-10-10

    IPC分类号: G06F9312

    摘要: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译: 计算机的浮点单元包括浮点计算单元,浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时,可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    Methods and apparatus for handling and storing bi-endian words in a floating-point processor
    2.
    发明授权
    Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权
    用于在浮点处理器中处理和存储双向字的方法和装置

    公开(公告)号:US06212539B1

    公开(公告)日:2001-04-03

    申请号:US09169483

    申请日:1998-10-10

    IPC分类号: G06F700

    CPC分类号: G06F7/768 G06F7/483

    摘要: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译: 计算机的浮点单元包括浮点计算单元,浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时,可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    Methods and apparatus for efficient control of floating-point status
register
    3.
    发明授权
    Methods and apparatus for efficient control of floating-point status register 有权
    浮点状态寄存器的有效控制方法和装置

    公开(公告)号:US6151669A

    公开(公告)日:2000-11-21

    申请号:US169481

    申请日:1998-10-10

    摘要: A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译: 计算机的浮点单元包括浮点计算单元,浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时,可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    Methods and apparatus for controlling exponent range in floating-point calculations
    4.
    发明授权
    Methods and apparatus for controlling exponent range in floating-point calculations 有权
    用于控制浮点运算中指数范围的方法和装置

    公开(公告)号:US06578059B1

    公开(公告)日:2003-06-10

    申请号:US09169669

    申请日:1998-10-10

    IPC分类号: G06F748

    摘要: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

    摘要翻译: 计算机的浮点单元包括浮点计算单元,浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时,可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。

    System and method for deferring exceptions generated during speculative execution
    5.
    发明授权
    System and method for deferring exceptions generated during speculative execution 有权
    用于推迟在投机执行期间产生的异常的系统和方法

    公开(公告)号:US06301705B1

    公开(公告)日:2001-10-09

    申请号:US09164327

    申请日:1998-10-01

    IPC分类号: G06F945

    CPC分类号: G06F9/3865 G06F9/3842

    摘要: The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.

    摘要翻译: 本发明一般涉及用于支持对包括非投机和推测指令的中央处理单元(CPU)的指令集的推测性执行的系统和方法。 根据本发明的一个方面,一种方法包括以下步骤:评估程序的指令以确定各个指令是推测性还是非推测性的,并且评估每个推测性指令以确定其是否产生异常。 对于产生异常的每个推测性指令,该方法然后将延迟异常令牌(DET)编码为CPU的寄存器的未使用的寄存器值。 根据本发明的另一方面,提供了一种系统,该系统包括被配置为评估指令集的指令以确定各个指令是推测性还是非推测性的电路。 系统还包括被配置为评估每个推测性指令以确定其是否产生异常的电路。 最后,系统还包括被配置为将延迟异常令牌(DET)编码为(CPU的)寄存器的未使用寄存器值的电路。

    Partitioned memory with shared memory resources and configurable functions

    公开(公告)号:US11221764B2

    公开(公告)日:2022-01-11

    申请号:US14503382

    申请日:2014-09-30

    摘要: A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The memory device includes a memory block having a plurality of banks, wherein each of the banks has a plurality of memory cells, and wherein the memory block has multiple ports. An output interface provides data on a second plurality of serial links. A cache coupled to the IO interface and to the plurality of banks, stores write data designated for a given memory cell location when the given memory cell location is currently being accessed, thereby avoiding a collision. Memory device includes one or more memory access controllers (MACs) coupled to the memory block and one or more arithmetic logic units (ALUs) coupled to the MACs. The ALUs perform one or more operations on data prior to the data being transmitted out of the IC via the IO, such as read/modify/write or statistics or traffic management functions, thereby reducing congestion on the serial links and offloading appropriate operations from the host to the memory device.

    Composting apparatus
    7.
    发明授权
    Composting apparatus 有权
    堆肥设备

    公开(公告)号:US08940529B2

    公开(公告)日:2015-01-27

    申请号:US13161889

    申请日:2011-06-16

    申请人: Michael Morrison

    发明人: Michael Morrison

    摘要: A composting apparatus comprising a container for receiving material to be composted a base member in the apparatus for supporting material to be composted and the compost when formed, the base having a curved lower wall and an upper opening to define a volume for receiving a drainage medium, a leachate chamber formed in the wall so that when leachate forms, the leachate is able to flow through the medium into the chamber; and an outlet from the chamber for supplying the leachate to the outside of the container.

    摘要翻译: 一种堆肥设备,包括用于接收待堆肥材料的容器,所述容器用于在用于支撑待堆肥的材料的装置中,并且当形成时堆肥,所述基座具有弯曲的下壁和上开口,以限定用于接收排水介质的容积 ,形成在壁中的渗滤液室,使得当渗滤液形成时,渗滤液能够流过介质进入室; 以及来自所述室的出口,用于将所述渗滤液供应到所述容器的外部。

    DIGITAL AUDIO AND VIDEO RECORDING AND STORAGE SYSTEM AND METHOD
    8.
    发明申请
    DIGITAL AUDIO AND VIDEO RECORDING AND STORAGE SYSTEM AND METHOD 审中-公开
    数字音频和视频记录和存储系统和方法

    公开(公告)号:US20120020638A1

    公开(公告)日:2012-01-26

    申请号:US13219951

    申请日:2011-08-29

    IPC分类号: H04N5/77

    摘要: An integrated apparatus is disclosed that can directly connect to a portable digital video camera and can record uncompressed video and audio data, along with associated metadata, in the field and elsewhere. Most preferably, the integrated apparatus includes a removable, recordable, reusable digital magazine that may be mounted. Most preferably, the integrated apparatus also supports a variety of input and output formats, and the apparatus may be easily connected to other computing systems, either directly or through network connections, wired or wireless. The digital magazine can be mounted in a variety of docking stations and can be directly connected to a network, allowing the video and audio data to be easily stored and transferred.

    摘要翻译: 公开了可以直接连接到便携式数字摄像机并且可以在现场和其他地方记录未压缩的视频和音频数据以及关联的元数据的集成设备。 最优选地,集成装置包括可安装的可拆卸的,可记录的可重复使用的数字盒。 最优选地,集成装置还支持各种输入和输出格式,并且该装置可以直接地或通过有线或无线的网络连接容易地连接到其他计算系统。 数字杂志可以安装在各种对接站中,可以直接连接到网络,允许视频和音频数据容易地存储和传输。

    Pressure control valve having an asymmetric valving structure
    9.
    发明授权
    Pressure control valve having an asymmetric valving structure 有权
    具有不对称阀结构的压力控制阀

    公开(公告)号:US07779863B2

    公开(公告)日:2010-08-24

    申请号:US11824540

    申请日:2007-06-29

    IPC分类号: F15B13/04

    摘要: The present invention describes, generally, a method and system for controlling the dynamics of an actuatable load functioning or operable within a servo or servo-type system, wherein the dynamics of the load are controlled by way of a unique asymmetric pressure control valve configured to provide intrinsic pressure regulation. The asymmetric pressure control valve, which may be referred to as a dynamic pressure regulator because of its capabilities, utilizes different sized free floating spools that are physically independent of one another and freely supported in interior cavities of respective corresponding different sized valving components that make up the valve body to regulate the pressures acting within the overall system between the control or pilot pressure and the load or load pressure. The dual spools of the pressure control valve, although physically independent of one another, function in cooperation with one another in an attempt to maintain a state of equilibrium in the system, namely to keep pressure acting on or within the actuator (the load pressure), or the feedback pressure corresponding to the load pressure, the same as the control or pilot pressure. Moreover, pressure regulation and control is intrinsic to the asymmetric pressure control valve because of the configuration and function of the dual spools and the feedback system acting on the spools, thus eliminating the need for electronically or mechanically user controlled systems.

    摘要翻译: 本发明总体上描述了一种用于控制在伺服或伺服型系统中起作用或可操作的可致动负载的动力学的方法和系统,其中负载的动力学通过独特的非对称压力控制阀来控制, 提供内在的压力调节。 不对称压力控制阀由于其功能而被称为动态压力调节器,它利用不同尺寸的自由浮动阀芯,它们在物理上彼此独立并且自由地支撑在组成相应不同尺寸阀门部件的内腔中 阀体调节在整个系统内作用于控制或先导压力与负载或负载压力之间的压力。 压力控制阀的双线轴虽然在物理上彼此独立,但彼此配合起作用,以维持系统中的平衡状态,即保持作用在致动器上或其内的压力(负载压力) ,或与负载压力相对应的反馈压力,与控制或先导压力相同。 此外,由于双线轴和作用在线轴上的反馈系统的配置和功能,压力调节和控制对于非对称压力控制阀是固有的,因此无需电子或机械用户控制的系统。

    Retaining washer for threaded fasteners
    10.
    发明授权
    Retaining washer for threaded fasteners 有权
    螺纹紧固件保持垫圈

    公开(公告)号:US07674080B2

    公开(公告)日:2010-03-09

    申请号:US11247260

    申请日:2005-10-12

    IPC分类号: F16B39/02

    摘要: The present invention provides a retaining washer for retaining threaded fasteners, such as bolts, that have been inadvertently loosened, in use. The invention finds particular application in gas turbine engines and in aircraft in general where wire locking of threaded fasteners has traditionally been employed. The washer (10) comprises a base member (14) having a plurality of apertures (18) each for receiving the shank of a respective bolt (20) or stud part of a threaded fastener, and engagement means (16) extending from the base member for engagement with respective bolt head or nut parts of the fasteners to retain the said head or nut parts with respect to the washer in the event of inadvertent loosening. The said engagement means is deformable between an open configuration which enables access to the bolt head or nut parts of the fasteners for tightening and/or removal thereof and a closed configuration in which the bolt head or nut part are captively retained with the washer.

    摘要翻译: 本发明提供了一种用于在使用中保持螺纹紧固件(例如螺栓)的保持垫圈,其被不经意地松动。 本发明特别适用于燃气涡轮发动机和飞机,通常在传统上采用螺纹紧固件的电线锁定。 垫圈(10)包括具有多个孔(18)的基部构件(14),每个孔用于接收螺纹紧固件的相应螺栓(20)或螺柱部分的柄,以及从底座延伸的接合装置(16) 用于与紧固件的相应螺栓头或螺母部分接合以在发生无意松动的情况下相对于垫圈保持所述头部或螺母部分。 所述接合装置可以在打开构造之间变形,该打开构造能够接近用于紧固和/或移除紧固件的螺栓头或螺母部分,以及闭合构造,其中螺栓头部或螺母部分被固定在垫圈上。