摘要:
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要:
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要:
A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要:
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要:
The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.
摘要:
A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The memory device includes a memory block having a plurality of banks, wherein each of the banks has a plurality of memory cells, and wherein the memory block has multiple ports. An output interface provides data on a second plurality of serial links. A cache coupled to the IO interface and to the plurality of banks, stores write data designated for a given memory cell location when the given memory cell location is currently being accessed, thereby avoiding a collision. Memory device includes one or more memory access controllers (MACs) coupled to the memory block and one or more arithmetic logic units (ALUs) coupled to the MACs. The ALUs perform one or more operations on data prior to the data being transmitted out of the IC via the IO, such as read/modify/write or statistics or traffic management functions, thereby reducing congestion on the serial links and offloading appropriate operations from the host to the memory device.
摘要:
A composting apparatus comprising a container for receiving material to be composted a base member in the apparatus for supporting material to be composted and the compost when formed, the base having a curved lower wall and an upper opening to define a volume for receiving a drainage medium, a leachate chamber formed in the wall so that when leachate forms, the leachate is able to flow through the medium into the chamber; and an outlet from the chamber for supplying the leachate to the outside of the container.
摘要:
An integrated apparatus is disclosed that can directly connect to a portable digital video camera and can record uncompressed video and audio data, along with associated metadata, in the field and elsewhere. Most preferably, the integrated apparatus includes a removable, recordable, reusable digital magazine that may be mounted. Most preferably, the integrated apparatus also supports a variety of input and output formats, and the apparatus may be easily connected to other computing systems, either directly or through network connections, wired or wireless. The digital magazine can be mounted in a variety of docking stations and can be directly connected to a network, allowing the video and audio data to be easily stored and transferred.
摘要:
The present invention describes, generally, a method and system for controlling the dynamics of an actuatable load functioning or operable within a servo or servo-type system, wherein the dynamics of the load are controlled by way of a unique asymmetric pressure control valve configured to provide intrinsic pressure regulation. The asymmetric pressure control valve, which may be referred to as a dynamic pressure regulator because of its capabilities, utilizes different sized free floating spools that are physically independent of one another and freely supported in interior cavities of respective corresponding different sized valving components that make up the valve body to regulate the pressures acting within the overall system between the control or pilot pressure and the load or load pressure. The dual spools of the pressure control valve, although physically independent of one another, function in cooperation with one another in an attempt to maintain a state of equilibrium in the system, namely to keep pressure acting on or within the actuator (the load pressure), or the feedback pressure corresponding to the load pressure, the same as the control or pilot pressure. Moreover, pressure regulation and control is intrinsic to the asymmetric pressure control valve because of the configuration and function of the dual spools and the feedback system acting on the spools, thus eliminating the need for electronically or mechanically user controlled systems.
摘要:
The present invention provides a retaining washer for retaining threaded fasteners, such as bolts, that have been inadvertently loosened, in use. The invention finds particular application in gas turbine engines and in aircraft in general where wire locking of threaded fasteners has traditionally been employed. The washer (10) comprises a base member (14) having a plurality of apertures (18) each for receiving the shank of a respective bolt (20) or stud part of a threaded fastener, and engagement means (16) extending from the base member for engagement with respective bolt head or nut parts of the fasteners to retain the said head or nut parts with respect to the washer in the event of inadvertent loosening. The said engagement means is deformable between an open configuration which enables access to the bolt head or nut parts of the fasteners for tightening and/or removal thereof and a closed configuration in which the bolt head or nut part are captively retained with the washer.