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公开(公告)号：US20130109330A1
公开(公告)日：2013-05-02
申请号：US13282354
申请日：2011-10-26
Applicant: Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
Inventor： Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
IPC: H04B1/40
Abstract: Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.
Abstract translation: 示例性实施例涉及收发器内的阻抗平衡。 设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。 此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。 该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。
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公开(公告)号：US20100244971A1
公开(公告)日：2010-09-30
申请号：US12436265
申请日：2009-05-06
Applicant: Kevin H. Wang , Saru Palakurty , Frederic Bossu
Inventor： Kevin H. Wang , Saru Palakurty , Frederic Bossu
IPC: H03L7/099
CPC classification number: G04F10/005
Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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公开(公告)号：US10044381B2
公开(公告)日：2018-08-07
申请号：US13584273
申请日：2012-08-13
Applicant: Mark Vernon Lane , Chang-Ho Lee , Christian Holenstein , Mahim Ranjan , Praveen-Kumar Sampath , Frederic Bossu , Sumit Verma , Wesley Alan Sampson
Inventor： Mark Vernon Lane , Chang-Ho Lee , Christian Holenstein , Mahim Ranjan , Praveen-Kumar Sampath , Frederic Bossu , Sumit Verma , Wesley Alan Sampson
IPC: H04B1/04
Abstract: Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band 40) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use.
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公开(公告)号：US08098085B2
公开(公告)日：2012-01-17
申请号：US12436265
申请日：2009-05-06
Applicant: Kevin H. Wang , Saru Palakurty , Frederic Bossu
Inventor： Kevin H. Wang , Saru Palakurty , Frederic Bossu
IPC: H03D13/00
CPC classification number: G04F10/005
Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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公开(公告)号：US20090221235A1
公开(公告)日：2009-09-03
申请号：US12366441
申请日：2009-02-05
Applicant: Steven C. Ciccarelli , Frederic Bossu , Vladimir Aparin , Kevin H. Wang
Inventor： Steven C. Ciccarelli , Frederic Bossu , Vladimir Aparin , Kevin H. Wang
CPC classification number: H03L7/1974
Abstract: Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
Abstract translation: 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。
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Patent Agency Ranking
公开(公告)号：US20090154595A1
公开(公告)日：2009-06-18
申请号：US12259178
申请日：2008-10-27
Applicant: Ojas M. Choksi , Frederic Bossu
Inventor： Ojas M. Choksi , Frederic Bossu
IPC: H04L27/00
CPC classification number: H04L5/1461 , H03D3/009 , H03M1/1019 , H03M1/66 , H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
Abstract: Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.
Abstract translation: 提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。 在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。 在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。 还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。 还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。
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公开(公告)号：US09362958B2
公开(公告)日：2016-06-07
申请号：US13411444
申请日：2012-03-02
Applicant: Prasad Srinivasa Siva Gudem , Gurkanwal Singh Sahota , Li-chung Chang , Christian Holenstein , Frederic Bossu
Inventor： Prasad Srinivasa Siva Gudem , Gurkanwal Singh Sahota , Li-chung Chang , Christian Holenstein , Frederic Bossu
CPC classification number: H04B1/0057 , H04B7/04
Abstract: A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.
Abstract translation: 描述了被配置为接收多载波信号的无线通信设备。 无线通信设备包括单芯片信号分离载波聚合接收机架构。 单芯片信号分离载波聚合接收机架构包括主天线，辅助天线和收发芯片。 单芯片信号分离载波聚合接收机架构重用同步混合双接收机路径。
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公开(公告)号：US09083441B2
公开(公告)日：2015-07-14
申请号：US13282354
申请日：2011-10-26
Applicant: Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
Inventor： Gurkanwal Singh Sahota , Frederic Bossu , Berke Cetinoneri
Abstract: Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.
Abstract translation: 示例性实施例涉及收发器内的阻抗平衡。 设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。 此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。 该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。
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公开(公告)号：US08929840B2
公开(公告)日：2015-01-06
申请号：US12209164
申请日：2008-09-11
Applicant: Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
Inventor： Sankaran Aniruddhan , Chiewcharn Narathong , Sriramgopal Sridhara , Ravi Sridhara , Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
CPC classification number: H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。 在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。
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公开(公告)号：US20120081185A1
公开(公告)日：2012-04-05
申请号：US13316621
申请日：2011-12-12
Applicant: Kevin H. Wang , Saru Palakurty , Frederic Bossu
Inventor： Kevin H. Wang , Saru Palakurty , Frederic Bossu
CPC classification number: G04F10/005
Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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