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公开(公告)号：US20090221235A1
公开(公告)日：2009-09-03
申请号：US12366441
申请日：2009-02-05
CPC分类号： H03L7/1974
摘要： Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
摘要翻译： 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。
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公开(公告)号：US09287886B2
公开(公告)日：2016-03-15
申请号：US12366441
申请日：2009-02-05
CPC分类号： H03L7/1974
摘要： Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
摘要翻译： 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。
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公开(公告)号：US20100244971A1
公开(公告)日：2010-09-30
申请号：US12436265
申请日：2009-05-06
申请人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
发明人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
IPC分类号： H03L7/099
CPC分类号： G04F10/005
摘要： A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
摘要翻译： 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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公开(公告)号：US08098085B2
公开(公告)日：2012-01-17
申请号：US12436265
申请日：2009-05-06
申请人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
发明人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
IPC分类号： H03D13/00
CPC分类号： G04F10/005
摘要： A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
摘要翻译： 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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公开(公告)号：US20120081185A1
公开(公告)日：2012-04-05
申请号：US13316621
申请日：2011-12-12
申请人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
发明人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
CPC分类号： G04F10/005
摘要： A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
摘要翻译： 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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公开(公告)号：US08878613B2
公开(公告)日：2014-11-04
申请号：US13316621
申请日：2011-12-12
申请人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
发明人： Kevin H. Wang , Saru Palakurty , Frederic Bossu
IPC分类号： H03L7/093
CPC分类号： G04F10/005
摘要： A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.
摘要翻译： 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。
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公开(公告)号：US08639205B2
公开(公告)日：2014-01-28
申请号：US12052657
申请日：2008-03-20
IPC分类号： H04B1/26
CPC分类号： H04W52/0206 , H03G3/20 , H04B1/16
摘要： An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.
摘要翻译： 公开的示例性实施例包括具有多个输入引线的混合器; 耦合到混合器的第一输入引线的第一退化阻抗元件; 耦合到混合器的第二输入引线的第二退化阻抗元件; 以及本地振荡器（LO）系统，其包括多个占空比模式以产生混频器的LO信号，本地振荡器系统基于混频器的第一增益状态在第一占空比中工作，并且在第二占空比 基于混频器的第二增益状态。
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公开(公告)号：US08615205B2
公开(公告)日：2013-12-24
申请号：US12259178
申请日：2008-10-27
申请人： Ojas M. Choksi , Frederic Bossu
发明人： Ojas M. Choksi , Frederic Bossu
IPC分类号： H03C1/62
CPC分类号： H04L5/1461 , H03D3/009 , H03M1/1019 , H03M1/66 , H04L27/0014 , H04L2027/0016 , H04L2027/0018 , H04L2027/0024
摘要： Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.
摘要翻译： 提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。 在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。 在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。 还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。 还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。
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公开(公告)号：US20130109330A1
公开(公告)日：2013-05-02
申请号：US13282354
申请日：2011-10-26
IPC分类号： H04B1/40
摘要： Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.
摘要翻译： 示例性实施例涉及收发器内的阻抗平衡。 设备可以包括具有耦合到发射路径的第一侧和耦合到接收路径的第二侧的变压器。 此外，设备可以包括耦合到第一侧的第一部分并被配置为耦合到天线的天线调谐网络。 该装置还可以包括耦合到第一侧的第二部分并被配置为被调整以使调节单元处的阻抗基本上等于天线调谐网络处的阻抗的调节单元。
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公开(公告)号：US20100240323A1
公开(公告)日：2010-09-23
申请号：US12407700
申请日：2009-03-19
申请人： Dongjiang Qiao , Frederic Bossu
发明人： Dongjiang Qiao , Frederic Bossu
CPC分类号： G06F1/06 , H03K23/667 , H03K23/68
摘要： A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.
摘要翻译： 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。
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